參數(shù)資料
型號(hào)： VSC8163
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 數(shù)字傳輸電路
英文描述： OC-48 16:1 SONET/SDH MUX with Clock Generator
中文描述： MUX/DEMUX, PQFP128
封裝： 14 X 20 MM, HEAT SINK, PLASTIC, QFP-128
文件頁(yè)數(shù)： 8/20頁(yè)
文件大小： 191K
代理商： VSC8163
VITESSE
VSC8163
OC-48 16:1 SONET/SDH
MUX with Clock Generator
Preliminary Data Sheet
Page 8
G52216-0, Rev 3.3
01/05/00
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Table 1: AC Characteristics
Parameters
Description
Min
Typ
Max
Units
Conditions
T
DSU
Data setup time to the rising
edge of CLK16I+
Data hold time after the
rising edge of CLK16+
0.75
—
—
ns
T
DH
1.0
—
—
ns
T
DOR
,T
DOF
DO± rise and fall time
—
—
120
ps
20% to 80% into 100
load
See Figure 6
See Figures 3 and 4
t
CLKR
, t
CLKF
CLK16O
D
CLKI
D
RCK
D
CLKO
D
CLK16O± rise and fall times
CLK16O± duty cycle
CLK16I± duty cycle
Reference clock duty cycle
CLKO duty cycle
—
40
30
40
40
—
—
—
—
—
250
60
70
60
60
ps
%
%
%
%
Assuming 10% distortion of CLKO
CLKO
PER
CLKO period
—
401.9
—
ps
SONET based 77.76MHz or
155.52MHz reference clock
SONET based 77.76MHz or
155.52MHz reference clock
Inverting CLKO will switch (approx)
t
SET
and t
HOLD
values.
Inverting CLKO will switch (approx)
t
SET
and t
HOLD
values.
CLK16O
PER
CLK16O period
—
6.4
—
ns
t
SET
DO setup time with respect
to rising CLKO edge
DO hold time with respect to
rising CLKO edge
—
90
—
ps
t
HOLD
—
310
—
ps
Clock Multiplier Performance
T
DJ
Output data jitter
—
—
4
ps
rms, tested to SONET specification
(12kHz to 20MHz) with 2ps rms jitter
on REFCLK.
rms, tested to SONET specification
(12kHz to 20MHz) with 2ps rms jitter
on REFCLK.
Exceeds SONET/SDH mask
T
CJ
Output clock jitter
—
—
4
ps
Jitter
tol
Jitter tolerance
Tuning Range
—
-100
—
—
—
ppm
+100
相關(guān)PDF資料
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VSC8164QR 制造商:Vitesse Semiconductor Corporation 功能描述:
VSC8166 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
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