參數(shù)資料
型號(hào)： VSC8162
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
中文描述： MUX/DEMUX, PQFP128
封裝： HEAT SINK, PLASTIC, QFP-128
文件頁(yè)數(shù)： 11/20頁(yè)
文件大?。?/td> 151K
代理商： VSC8162
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 11
9/14/98
VITESSE
Advance Product Information
VSC8162
2.488 Gbit/sec SONET/SDH
1:16 Demux with Clock Recovery
G52209-0, Rev. 2.0
Table 4:
PLL Parameters
Figure 12:
VSC8162 Jitter Mask Specification
slope = -20 dB/decade
a. Measured at the HS clock output for jitter in the 12 kHz to 20 MHz band. Assume 1.2 ps rms input data jitter
b. Error-free operation guaranteed when electrical input signal is subject to jitter specified by mask in Figure 9.
Parameters
Description
Min
Typ
Max
Units
Conditions
RC
d
RC
f
f
RC
t
ACQ
t
set
t
clr
REFCK Duty Cycle
45
—
55
%
—
REFCK Frequency
REFCK Frequency Tolerance
Acquisition time
Loss of Lock set time
Loss of Lock clear time
Maximum zero-timing-content
period
Jitter generation
a
Jitter tolerance
b
—
-100
—
2.3
125
19.44
—
—
—
—
—
MHz
ppm
μ
s
μ
s
μ
s
—
—
With valid reference clock
From data interruption
From data restoration
+100
20
100
250
t
density
—
1200
—
UI
For 0 BER
t
jitter
t
tolerance
—
3.6
4.0
ps rms
—
Exceeds mask in Figure 9
—
sinusoidal
input
jitter
amplitude
(UI p-p)
30
15
3.0
0.30
frequency (Hz)
10
600
6k
100k
1000k
0.15
1.5
SONET/SDH Mask
VSC8162 Mask
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