參數(shù)資料
型號(hào)： VSC8116QP
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 數(shù)字傳輸電路
英文描述： TRANS NPN 40VCEO 50MA SMINI-3
中文描述： TRANSCEIVER, PQFP64
封裝： 10 X 10 MM, HEAT SPREADER, PLASTIC, QFP-64
文件頁(yè)數(shù)： 19/20頁(yè)
文件大?。?/td> 358K
代理商： VSC8116QP
G52220-0, Rev 4.1
1/8/00
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 19
VITESSE
Data Sheet
VSC8116
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Table 14: AC Coupling Component Values
TTL Input Structure
The TTL inputs of the VSC8116 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tol-
erances (see Table 11). The input structure, shown in Figure 12, uses a current limiter to avoid overdriving the
input FETs.
Layout of the High Speed Signals
The routing of the High Speed signals should be done using good high speed design practices. This would
include using controlled impedance lines (50 ohms) and keeping the distance between components to an abso-
lute minimum. In addition, stubs should be kept at a minimum as well as any routing discontinuities. This will
help minimize reflections and ringing on the high speed lines and insure the maximum eye opening. In addition
the output pull down resistor R2 should be placed as close to the VSC8116 pin as possible while the AC-cou-
pling capacitor C2 and the biasing resistors R3, R4 should be placed as close as possible to the optics input pin.
The same is true on the receive circuit side. Using small outline components and minimum pad sizes also helps
in reducing discontinuities.
Ground Planes
The ground plane for the components used in the High Speed interface should be continuous and not sec-
tioned in an attempt to provide isolation to various components. Sectioning of the ground planes tends to inter-
fere with the ground return currents on the signal lines. In addition, the smaller the ground planes the less
effective they are in reducing ground bounce noise and the more difficult to decouple. Sectioning of the positive
supplies can provide some isolation benefits.
Analog Power Supplies
Good analog design practices should be applied to the board design for the analog ground and power
planes. The dedicated PLL power (VDDA) and ground (VSSA) pins need to have quiet supply planes to mini-
mize jitter generation within the clock synthesis unit. This is accomplished by either using a ferrit bead or a C-
L-C choke (
π
filter).
Component
Value
Tolerance
R1
R2
R3
R4
270 ohms
75 ohms
68 ohms
190 ohms
5%
5%
1%
1%
10%
C1, C2, C3, C4
.01uf High Frequency
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