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參數(shù)資料
| 型號(hào)： | VSC7186 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | Quad Transceiver for Gigabit Ethernet |
| 中文描述： | 四千兆以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 232K |
| 代理商： | VSC7186 |
VITESSE
Advance Product Information
VSC7186
Quad Transceiver
for Gigabit Ethernet
Page 2
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012
805/388-3700
FAX: 805/987-5896
3/27/00
G52306-0, Rev. 2.0
Functional Description
Notation
In this document, each of the four channels are identified as Channel 0, 1, 2 or 3. When discussing a signal
on any specific channel, the signal will have the Channel number embedded in the name, i.e.
“
T
3
(0:9)
”
. When
referring to the common behavior of a signal which is used on each of the four channels, the notation
“
i
”
is used.
Differential signals, i.e. SOi+ and SOi-, may be referred to as a single signal, i.e. SOi, by dropping reference to
the
“
+
”
and
“
-
”
.
Clock Synthesizer
The VSC7186 Clock Multiplier Unit (CMU) multiplies the reference frequency provided on the RFC1
input by 10 to achieve a baud rate clock between 1.05 and 1.36 GHz. The RFC1 input is TTL. The on-chip PLL
uses a single external 0.1uF capacitor, connected between CAP0 and CAP1, to control the Loop Filter. This
capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working voltage rating and a
good temperature coefficient, i.e., NPO is preferred but X7R may be acceptable. These capacitors are used to
minimize the impact of common mode noise on the Clock Multiplier Unit, especially power supply noise.
Higher value capacitors provide better robustness in systems. NPO is preferred because if an X7R capacitor is
used, the power supply noise sensitivity will vary with temperature.
For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor
between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to ground,
C3. Larger values are better but 0.1uF is adequate. However, if the designer cannot use a three capacitor circuit,
a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces.
Figure 1: Loop Filter Capacitors (Best Circuit)
Serializer
The VSC7186 accepts TTL input data as four parallel 10 bit characters on the Ti(0:9) buses which are
latched into the input registers on the rising edge of RFC1. The 10-bit parallel transmission character will be
serialized and transmitted on the SOi+/- PECL differential outputs at the baud rate with bit Ti0 (bit a) transmit-
ted first. User data should be encoded using 8b/10b or an equivalent code. The mapping to 10b encoded bit
nomenclature and transmission order is illustrated below, along with the recognized comma pattern.
CAP0
CAP1
C1
C2
C3
VSC7186
C1=C2=C3= >0.1uF
MultiLayer Ceramic
Surface Mount
NPO (Prefered) or X7R
5V Working Voltage Rating
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| VSC7212RG | 制造商: 功能描述: 制造商:undefined 功能描述: 制造商:VITESSA 功能描述: |
| VSC7214QV11 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fiber-Optic Transceiver |
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