參數(shù)資料
型號(hào): VSC7123
廠商: Vitesse Semiconductor Corporation.
英文描述: Rotary Switch; No. of Switch Positions:10; Circuitry:SPDT; Contact Current Max:1.5A; Indexing:30 ; Contact Rating:1.5A at 28VDC; Mounting Type:Panel; Number of Positions:10; Switch Features:30 degrees Indexing; Switch Function:SPDT
中文描述: 10位收發(fā)器,光纖通道和千兆以太網(wǎng)
文件頁(yè)數(shù): 14/18頁(yè)
文件大小: 208K
代理商: VSC7123
V
ELOCITY
TM
VITESSE
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Page 14
G52212-0, Rev 4.3
03/25/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
62, 61
TX+, TX-
OUTPUTS - Differential PECL (AC-coupling recommended):
These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is
HIGH, TX+ is HIGH and TX- is LOW.
OUTPUTS - TTL:
10-bit received character. Parallel data on this bus is clocked out on the rising edges of
RCLK and RCLKN. R0 is the first bit received on RX+/RX-.
INPUT - TTL:
LOW for normal operation. When HIGH, an internal loopback path from the transmitter to
the receiver is enabled. TX+ is held HIGH and TX- is held LOW.
INPUTS - Differential PECL (AC-coupling recommended):
The serial receive data inputs selected when EWRAP is LOW. Internally biased to VDD/2,
with 3.3K
resistors from each input pin to VDD and GND.
OUTPUT - Complementary TTL:
Recovered clocks derived from 1/20
th
of the RX+/- data stream. Each rising transition of
RCLK or RCLKN corresponds to a new word on R(0:9).
INPUT - TTL:
Enables COMDET and word resynchronization when HIGH. When LOW, keeps current
word alignment and disables COMDET.
OUTPUT - TTL:
This output goes HIGH for half of an RCLK period to indicate that R(0:9) contains a comma
character (
0011111XXX
). COMDET will go HIGH only during a cycle when RCLKN is
rising. COMDET is enabled by ENCDET being HIGH.
OUTPUT - TTL
SIGnal DETect. This output goes HIGH when the RX input contains a valid Fibre Channel or
Gigabit Ethernet signal. A LOW indicates an invalid signal.
ANALOG: Differential capacitor for the CMU
s VCO, 0.1
μ
F nominal.
INPUT - TTL: JTAG clock input. Not normally connected.
INPUT - TTL: JTAG data input. Not normally connected.
INPUT - TTL: JTAG mode select input. Normally tied to V
DDD
INPUT - TLL: JTAG reset input. Tie to V
SSD
for normal operation.
OUTPU - TTL: JTAG data output. Normally tri-stated.
Analog Power Supply
Analog Ground
45,44,43,41
40,39,38,36
35,34
R0,R1,R2,R3
R4,R5,R6,R7
R8,R9
19
EWRAP
54, 52
RX+, RX-
31, 30
RCLK,
RCLKN
24
ENCDET
47
COMDET
26
SIGDET
16, 17
49
48
55
56
27
18
15
5,10,20,23
28,50,57,59
1,14,21,25
51,58,64
29, 37, 42
32, 33, 46
60,63
53
CAP0, CAP1
TCK
TDI
TMS
TRSTN
TDO
VDDA
VSSA
VDDD
Digital Logic Power Supply
VSSD
Digital Logic Ground
VDDT
VSST
VDDP
N/C
TTL Output Power Supply
TTL Output Ground
PECL I/O Power Supply
No internal connection
Pin #
Name
Description
相關(guān)PDF資料
PDF描述
VSC7123RD 10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
VSC7123QU Development kit; Kit Contents:Evaluation Board; For Use With:CS4955A; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No
VSC7124 Rotary Switch; No. of Switch Positions:4; Circuitry:DPDT; Contact Current Max:1.5A; Indexing:30 ; Contact Rating:1.5A at 28VDC; Mounting Type:Panel; Number of Positions:4; Switch Features:30 degrees Indexing; Switch Function:DPDT
VSC7124QM Quad Port Bypass Circuit
VSC7125 Rotary Switch; Contact Current Max:1.5A; No. of Poles:4; No. of Switch Positions:11; Indexing:30 ; No. of Decks:4; Switch Terminals:Solder Lug; Circuitry:SPDT; Mounting Type:Panel; Switch Features:30 degrees Indexing RoHS Compliant: Yes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VSC7123QN 制造商:VITE 功能描述:
VSC7123QN/C 制造商:Vitesse Semiconductor Corporation 功能描述:
VSC7123QU 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
VSC7123RD 制造商:Vitesse Semiconductor Corporation 功能描述:
VSC7123RD2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm