參數(shù)資料
型號(hào)： VS8061FC
廠商： VITESSE SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, CQFP52
封裝： HEAT SINK, CERAMIC, LDCC-52
文件頁(yè)數(shù)： 19/20頁(yè)
文件大小： 409K
代理商： VS8061FC
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC8061/VSC8062
2.5 Gb/s 16-Bit Multiplexer/
Demultiplexer Chipset
Page 8
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
6/22/99
G52069-0, Rev. 4.1
Coupling for Inputs
Figure 7: AC-Coupling for DCLK, DCLKN Inputs
DCLK, DCLKN Inputs
Internal biasing will position the reference voltage of approximately -1.32V on both the true and comple-
ment inputs. This input can either be DC-coupled or AC-coupled; it can also be driven single-ended or differen-
tially. Figure 7 shows the configuration for a single-ended, AC-coupling operation. In the case of direct
coupling and single-ended input, it is recommended that a stable V
REF for ECL levels be used for the comple-
mentary input.
High Speed Clock and Serial Data Inputs
It is recommended that all high speed clock and serial data inputs (i.e. CLK/CLKN for the VS8061; DI/DIN
and CLK/CLKN for the VS8062) be AC-coupled. Figure 8 shows the configuration for a single-ended AC-cou-
pling operation.
In most situations these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. The following is to assist in this application.
All serial data and clock inputs have the same circuit topology, as shown in figure 8. The reference voltage
is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part,
the mid-point of the input signal swing should be centered about this reference voltage and not exceed the max-
imum allowable amplitude. For single-ended, DC-coupling operations, it is recommended that the user provides
an external reference voltage which has better temperature and power supply noise rejection than the on-chip
V
TT
DCLK
DCLKN
V
CC = GND
V
TT = -2V
-1.32V
R
| | = 1k
C
IN
C
SE
V
TT
Chip Boundary
C
IN TYP = 0.1F
C
SE TYP = 0.1F for single ended applications. (Capacitor values are
Z
O
R
T = ZO
selected for DCLK = 155 Mb/s.)
相關(guān)PDF資料
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