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VP 510
2
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
R7:0
G7:0
B7:0
Y7:0
C7:0
D7:0
A4:0
CLK
HREF
HDLY
FI
FO
CRI
CRO
OEN
CS
RD
WR
RES
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
I
O
I
O
I
I
I
I
I
Unsigned Red data. Range may be changed by the RAM look up table
Unsigned Green data. Range may be changed by the RAM look up table
Unsigned Blue data. Range may be changed by the RAM look up table
Unsigned Luminance data in or out. Range is user definable
Two's complement or offset binary multiplexed chrominance data. Range is user definable
Host data bus used for reading or writing
Host Address Bus. Matrix coefficients and the control register are directly addressable
External line locked clock. All inputs and outputs are referenced to the rising edge
Horizontal or Composite reference used as a start of line indicator and to clear the FIR filters
HREF input delayed by the 39 clock delay to a correctly filtered output
Input Flag as defined by the user. No internal operation.
FI delayed by the 39 clock delay to a correctly filtered output
An input which indicates that valid luminance and chrominance data is present
An output which indicates that valid luminance and chrominance data is on the output pins
Active low output enable for the tristate bus. Used in conjunction with a Control Register bit
Active low Chip Select from the host system
Active low request from the host to read the matrix coefficients and RAM contents
Active low request from the host to write to the device
Asynchronous low reset used to initialise the device. Must be present for at least 1024 clock periods
LOOK UP TABLES
When the device is configured to produce chrominance
and luminance outputs from RGB inputs, each of the three
look up tables is addressed by its appropriate colour bus. Any
changes to the data thus occur before the colour space
conversion. Typically the look up tables are used to provide
gamma correction to linear RGB inputs, and / or to limit the
range of the inputs. The coefficients in the conversion matrix
are usually defined to expect either a range of 1 - 254 or 16 -
235, when converting to Cr and Cb chrominance values.
When the device is configured to produce RGB outputs,
the look up tables are positioned just before the output buses.
If linear outputs are required the tables can then be used to
remove the gamma correction which is produced by the
coefficients in the conversion matrix. They can also be used to
expand the range produced by the conversion matrix.
The RAM's are not dual ported and use by the host system
takes priority over pixel accessing. The RAM's are not directly
addressable from the host since the device only uses a 5 bit
address bus. Instead each RAM has an internal address
counter which must be cleared by writing to address decimal
27. Data is then sequentially written to the Red RAM by
supplying 256 bytes of data and address 28. Similarly using
address 29 will cause write operations to the green RAM, and
address 30 will cause write operations to the blue RAM. The
counters do not wrap around and must be reset by using
address 27 before further write or read operations are re-
quired. Read operations are mechanized in a similar manner
to write operations, except that a read strobe must be supplied
instead of a write strobe. Since each RAM has its own address
counter the red, green, and blue operations can be intermin-
gled on a byte by byte basis, rather than completing one colour
before starting the next.
Although host operations are asynchronous to the device
clock, this clock must be present to internally effect a read or
write operation. The read and write strobes are internally
synchronized to the clock, and the read strobe must be active
for at least five clock periods, and the write strobe for two clock
periods.
CONVERSION MATRIX
The 3 x 3 matrix multiplier performs the following basic
operation on three channels with identical sampling rates;
O/PA c1 c2 c3
O/PB = c4 c5 c6 X
O/PC c7 c8 c9
I/PA
I/PB
I/PC
When converting from RGB to colour difference informa-
tion, any decimation of the chrominance channels must be
done after the above operation. Conversely when producing
RGB data the chrominance channels must be interpolated
before the matrix operation. The configuration bit in the
Control Register takes care of this reorganization.
The coefficients C9:1 are loaded from the host system,
and are directly addressable using the 5 bits provided ( see
Table 1 ). Each coefficient must be loaded as two bytes since
it uses a total of 12 bits. The upper 4 bits in the most significant
byte are don't care values. If the loaded values are read back
by the host, these four bits will always be zero's, and are not
sign bits.
The 12 coefficient bits are comprised of 3 signed integer
and 9 fractional bits. This gives a decimal range of -4.00 to
approximately +3.998, with the fractional bits actually giving a
decimal resolution of 0.001953.
Pixel data going into the matrix multiplier uses a total of 13
bits; 10 signed integer bits plus 3 fractional bits. This additional
pixel accuracy is only obtained from the output of the interpo-
lating filters, where 10 integer bits are necessary to accommo-
date signed data with undershoot and overshoot beyond the
nominal gain.