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參數(shù)資料
| 型號(hào)： | VORTEX86SX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32-BIT x86 Embedded SoC |
| 中文描述： | 32位x86嵌入式系統(tǒng)芯片 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 2964K |
| 代理商： | VORTEX86SX |
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Vortex86SX
32-Bit x86 Embedded SoC
Vortex86SX Brief Datasheet
Version 1.001
14
z
COM2/PWM Interface (9 PINs)
PIN No.
Symbol
Type
Description
AF25
SIN2/PWM2CLK
I
COM2 Receive Data.
FIFO UART receiver serial data input signal.
PWM Timer2 Clock.
This pin is PWM timer2 external clock input when SB
register C0h bit2 is 1 (PINs for PWM).
COM2 Transmit Data.
FIFO UART transmitter serial data output from the
serial port.
PWM Timer0 Output.
This pin is PWM timer0 output when SB register C0h
bit2 is 1 (PINs for PWM).
Request to Send.
Active low Request to Send output for UART port.
A handshake output signal notifies the modem that the UART is ready to
transmit data. This signal can be programmed by writing to bit 1 of Modem
Control Register (MCR). The hardware reset will clear the RTS_n signal to be
inactive mode (high). It is forced to be inactive during the loop-mode
operation.
PWM Timer1 Output.
This pin is PWM timer1 output when SB register C0h
bit2 is 1 (PINs for PWM).
Clear to Send.
This active low input for the primary and secondary serial
ports. A handshake signal notifies the UART that the modem is ready to
receive data. The CPU can monitor the status of the CTS_n signal by reading
bit 4 of Modem Status Register (MSR). A CTS_n signal states the change
from low to high after the last MSR read sets bit 0 of the MSR to a “1”. If bit 3
of the Interrupt Enable Register is set, the interrupt is generated when CTS_n
changes the state. The CTS_n signal has no effect on the transmitter.
Note:
Bit 4 of the MSR is the complement of CTS_n.
PWM Timer1 Gate.
This pin is PWM timer1 gate mask when SB register C0h
bit2 is 1 (PINs for PWM).
Data Set Ready.
This active low input is for the UART ports. A handshake
signal notifies the UART that the modem is ready to establish the
communication link. The CPU can monitor the status of the DSR_n signal by
reading bit5 of the Modem Status Register (MSR). A DSR_n signal states the
change from low to high after the last MSR read sets bit1 of the MSR to a “1”.
If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when
DSR_n changes state.
Note:
Bit 5 of the MSR is the complement of DSR_n.
PWM Timer0 Gate.
This pin is PWM timer0 gate mask when SB register C0h
bit2 is 1 (PINs for PWM).
Data Carrier Detect.
This active low input is for the UART ports. A handshake
signal notifies the UART that the carrier signal is detected by the modem. The
CPU can monitor the status of the DCD_n signal by reading bit 7 of the
Modem Status Register (MSR). A DCD_n signal states the change from low to
high after the last MSR read sets bit 3 of the MSR to a “1”. If bit 3 of the
Interrupt Enable Register is set, the interrupt is generated when DCDJ
changes state.
Note:
Bit 7 of the MSR is the complement of DCD_n.
PWM Timer0 Clock.
This pin is PWM timer0 external clock input when SB
register C0h bit2 is 1 (PINs for PWM).
AE24
SOUT2/PWM0OUT
O
AD25
RTS2/PWM1OUT
O
AD26
CTS2/PWM1GATE
I
AE26
DSR2/PWM0GATE
I
AC26
DCD2/PWM0CLK
I
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