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參數資料
| 型號： | VG26S17400DJ-5 |
| 英文描述： | DRAM|FAST PAGE|4MX4|CMOS|SOJ|26PIN|PLASTIC |
| 中文描述： | 內存|快速頁面| 4MX4 |的CMOS | SOJ | 26PIN |塑料 |
| 文件頁數： | 10/25頁 |
| 文件大?。?/td> | 212K |
| 代理商： | VG26S17400DJ-5 |
Document:1G5-0126
Rev.1
Page 10
VIS
VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
AC Characteristics
(Ta = 0 to + 70°C, V
CC
= 5V
Test conditions
10% or 3.3V
10%, V
SS
= 0V) * 1, * 2, * 3, * 4
Output load : two TTL Loads and 100pF(V
CC
= 5.0V
10%)
one TTL Load and 100pF(V
CC
= 3.3V
Input timing reference levels :
10%)
V
IH
= 2.4V, V
lL
= 0.8V (V
CC
= 5.0V
Output timing reference levels :
10%); V
IH
= 2.0V, V
lL
= 0.8V (V
CC
= 3.3V
10%)
V
OH
= 2.0V, V
OL
= 0.8V (V
CC
= 5V
10%, 3.3V
10%)
Read, Write, Read - Modify - Write and Refresh Cycles
(Common Parameters)
Parameter
Symbol
t
RC
t
RP
t
CPN
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RAL
t
RSH
t
CSH
t
CRP
t
OED
t
T
t
REF
t
REF
t
CLZ
t
DZC
t
DZO
VG26 (V) (S) 17400D
-5
Max
Unit
Notes
-6
Min
Min
Max
Random read or write cycle time
90
-
110
-
ns
RAS precharge time
30
-
40
-
ns
CAS precharge time in normal mode
10
-
10
-
ns
RAS pulse width
50
10000
60
15
10000
ns
5
CAS pulse width
12
10000
10000
ns
6
Row address setup time
0
-
0
-
ns
Row address hold time
8
-
10
-
ns
Column address setup time
0
-
0
-
ns
7
Column address hold time
8
-
10
-
ns
RAS to CAS delay time
12
37
14
45
ns
8
RAS to column address delay time
10
25
12
30
ns
9
Column address to RAS lead time
25
-
30
-
ns
RAS hold time
13
-
15
-
ns
CAS hold time
50
-
60
-
ns
CAS to RAS precharge time
5
-
5
-
ns
10
OE to Din delay time
12
-
15
-
ns
Transition time (rise and fall)
1
50
1
50
ns
11
Refresh period
-
32
-
32
ms
Refresh period (S - Version)
-
128
-
128
ms
CAS to output in Low-Z
0
-
0
-
ns
CAS delay time from Din
0
-
0
-
ns
OE delay time from Din
0
-
0
-
ns
±
±
±
±
±
±
±
±
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