參數(shù)資料
型號(hào)： VCH162373ADL
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： 16-bit D-type transparent latch with 30 ohm series termination resistors; 5 V input/output tolerant; 3-state
中文描述： LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48
封裝： 7.50 MM, PLASTIC, SOT-370-1, SSOP-48
文件頁(yè)數(shù)： 2/17頁(yè)
文件大?。?/td> 112K
代理商： VCH162373ADL
2004 Feb 05
2
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30
series termination
resistors; 5 V tolerant inputs/outputs; 3-state
74LVC162373A;
74LVCH162373A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bushold (74LVCH162373A only)
High-impedance when V
CC
= 0 V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
40 to +85
°
C and
40 to +125
°
C.
DESCRIPTION
The 74LVC(H)162373A is a 16-bit D-type transparent
latch featuring separate D-type inputs for each latch and
3-state outputs for bus oriented applications. One latch
enable (pin nLE) input and one output enable (pin nOE)
are provided for each octal. Inputs can be driven from
either 3.3 or 5 V devices. In 3-state operation, outputs can
handle 5 V. These features allow the use of these devices
in a mixed 3.3 and 5 V environment.
The 74LVC(H)162373A consists of 2 sections of eight
D-type transparent latches with 3-state true outputs. When
pin nLE is HIGH, data at the corresponding data inputs
(pins nDn) enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time
its corresponding data inputs changes.
When pin nLE is LOW the latches store the information
that was present at the data inputs a set-up time preceding
the HIGH-to-LOW transition of pin nLE. When pin nOE is
LOW, the contents of the eight latches are available at the
outputs. When pin nOE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the nOE input
does not affect the state of the latches.
The 74LVCH162373A bushold data inputs eliminates the
need for external pull-up resistors to hold unused inputs.
The 74LVC(H)162373A is designed with 30
series
termination resistors in both high and low output stages to
reduce line noise.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nDn to nQn
propagation delay nLE to nQn
3-state output enable time nOE to nQn
3-state output disable time nOE to nQn C
L
= 50 pF; V
CC
= 3.3 V
input capacitance
power dissipation per latch
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
3.3
3.5
4.0
3.4
5.0
ns
ns
ns
ns
pF
t
PZH
/t
PZL
t
PHZ
/t
PLZ
C
I
C
PD
V
CC
= 3.3 V; notes 1 and 2
outputs enabled
outputs disabled
26
19
pF
pF
相關(guān)PDF資料
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