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參數(shù)資料
| 型號(hào)： | VCC6-RAG-200M000 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 200 MHz, LVPECL OUTPUT |
| 封裝： | ROHS COMPLIANT, CERAMIC, SMD, 6 PIN |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 232K |
| 代理商： | VCC6-RAG-200M000 |
VCC6-Q/R Series, 2.5 and 3.3v PECL Crystal Oscillator
Vectron International 267 Lowell Rd, Hudson NH 03051
Tel: 1-88-VECTRON-1
e-mail: vectron@vectron.com
Performance Characteristics
Table 1. Electrical Performance
Parameter
Symbol
Min
Typical
Maximum
Units
Frequency
fO
10
270
MHz
Supply Voltage
1, 3.3V Q option
2.5V R option
VDD
3.15
2.375
3.3
2.5
3.45
2.625
V
Supply Current
IDD
98
mA
Output Logic Levels, 0/70°C
Output Logic High
2
Output Logic Low
2
VOH
VOL
VDD-1.025
VDD-1.810
VDD-0.880
VDD-1.620
V
Output Logic Levels, -40/85°C
Output Logic High
2
Output Logic Low
2
VOH
VOL
VDD-1.085
VDD-1.830
VDD-0.880
VDD-1.555
V
Transition Times
Rise Time
2
Fall Time
2
tR
tF
600
ps
Symmetry or Duty Cycle
3
SYM
45
50
55
%
Operating temperature (ordering option)
TOP
-10/70 or –40/85
°C
Stability (ordering option)
4
deltaF/F
±25, ±50 or ±100
ppm
Jitter, 12kHz to 20MHz
5
Cycle to Cycle, rms
Cycle to Cycle, peak-peak
Period Jitter, rms
Period Jitter, peak-peak
0.3
4.8
38
2.7
23
0.7
pS
Output Enabled
6
VIH
0.7*VDD
V
Output Disabled
6
VIL
0.3*VDD
V
Output Enable/Disable time
tE/D
200
nS
Enable/Disable Leakage Current
IIL
±200
uA
Output Enable Pull-Up Resistor
6
Output Enabled
Output Disabled
33
1
Kohm
Mohm
1. A 0.01uF and a 0.1uF capacitor should be located as close to the supply as possible and terminated to ground.
2. Figure 1 defines these parameters. Figure 2 illustrates the operating conditions under which these parameters are tested and specified.
3. Symmetry is measured defined as On Time/Period.
4. Includes calibration tolerance, operating temperature, supply voltage variations, aging (40 degreesC/10 years) and shock and vibration (not under
operation).
5. Measurements made on a VCC6-QAB-155M520 using an Agilent E5052A for phase noise and LeCroy 8600, 25K samples for jitter.
6. Output will be enabled if Enable/Disable is left open. The pull resistor changes to a higher value, operating in a “power saving mode” when
Enable/Disable is set to a logic 0.
Figure 1. Output Waveform
Figure 2. Typical Output Test Conditions (25
±5°C)
80
%
Vs
20
%
t
F
t
R
Period
On Time
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