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參數(shù)資料
| 型號： | V827332K04S |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 2.5 VOLT 32M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE |
| 中文描述： | 2.5伏32M × 72配置高性能無緩沖ECC DDR SDRAM內(nèi)存模塊 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 277K |
| 代理商： | V827332K04S |
10
MOSEL VITELIC
V827332K04S
V827332K04S Rev. 1.6 March 2002
AC Characteristics
(AC operating conditions unless otherwise noted)
Parameter
Symbol
(PC1600)
(PC2100B)
(PC2100A)
Unit Note
Min
Max
Min
Max
Min
Max
Row Cycle Time
t
RC
60
-
65
-
70
-
ns
Auto Refresh Row Cycle Time
t
RFC
67
-
75
-
80
-
ns
Row Active Time
t
RAS
45
120K
48
120K
50
120K
ns
Row Address to Column Address Delay
t
RCD
18
-
20
-
20
-
ns
Row Active to Row Active Delay
t
RRD
14
-
15
-
15
-
ns
Column Address to Column Address Delay
t
CCD
1
-
1
-
1
-
CLK
Row Precharge Time
t
RP
18
-
20
-
20
-
ns
Write Recovery Time
t
WR
15
-
15
-
15
-
ns
Last Data-In to Read Command
t
DRL
1
-
1
-
1
-
CLK
Auto Precharge Write Recovery + Precharge Time
t
DAL
35
-
35
-
35
-
ns
System Clock Cycle Time
CAS Latency = 2.5
t
CK
7
12
7.5
12
8
12
ns
CAS Latency = 2
7.5
12
10
12
10
12
ns
Clock High Level Width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
CLK
Clock Low Level Width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
CLK
Data-Out edge to Clock edge Skew
t
AC
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
DQS-Out edge to Clock edge Skew
t
DQSCK
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
DQS-Out edge to Data-Out edge Skew
t
DQSQ
-
0.5
-
0.5
-
0.6
ns
Data-Out hold time from DQS
t
QH
t
HPmin
-0.75ns
-
t
HPmin
-0.75ns
-
t
HPmin
-0.75ns
-
ns
1
Clock Half Period
t
HP
t
CH/L
min
-
t
CH/L
min
-
t
CH/L
min
-
ns
1
Input Setup Time (fast slew rate)
t
IS
0.9
-
0.9
-
1.1
-
ns
2,3,5,6
Input Hold Time (fast slew rate)
t
IH
0.9
-
0.9
-
1.1
-
ns
2,3,5,6
Input Setup Time (slow slew rate)
t
IS
1.0
-
1.0
-
1.1
-
ns
2,4,5,6
Input Hold Time (slow slew rate)
t
IH
1.0
-
1.0
-
1.1
-
ns
2,4,5,6
Input Pulse Width
t
IPW
2.2
-
2.2
-
-
-
ns
6
Write DQS High Level Width
t
DQSH
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Write DQS Low Level Width
t
DQSL
0.4
0.6
0.4
0.6
0.4
0.6
CLK
CLK to First Rising edge of DQS-In
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
CLK
Data-In Setup Time to DQS-In (DQ & DM)
t
DS
0.5
-
0.5
-
0.6
-
ns
7
Data-in Hold Time to DQS-In (DQ & DM)
t
DH
0.5
-
0.5
-
0.6
-
ns
7
DQ & DM Input Pulse Width
t
DIPW
1.75
-
1.75
-
2
-
ns
Read DQS Preamble Time
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
CLK
Read DQS Postamble Time
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
CLK
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| V827332N04S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:2.5 VOLT 32M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE |
| V827332U04S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:2.5 VOLT 32M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE |
| V827432K24S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:2.5 VOLT 32M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE |
| V827464K24S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:2.5 VOLT 64M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE |
| V827464N24S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:2.5 VOLT 64M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE |
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