參數(shù)資料
型號(hào): V826532K04S
廠商: Mosel Vitelic, Corp.
英文描述: 2.5 VOLT 32M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE
中文描述: 2.5伏32M的高性能× 64 DDR SDRAM內(nèi)存模塊緩沖
文件頁數(shù): 9/14頁
文件大小: 268K
代理商: V826532K04S
MOSEL VITELIC
V826532K04S
9
V826532K04S Rev. 1.2 March 2002
DDR SDRAM MODULE I
DD
SPEC TABLE
* Module I
DD
was calculated on the basis of component I
DD
and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Symbol
B1
(DDR266@CL=2)
B0
(DDR266@ CL=2.5)
A1
(DDR200@CL=2)
Unit
Typical
Worst
Typical
Worst
Typical
Worst
IDD0
1210
1230
1210
1230
980
1050
mA
IDD1
1440
1530
1440
1530
1130
1250
mA
IDD2P
610
650
610
650
490
530
mA
IDD2F
770
850
770
850
650
690
mA
IDD2Q
690
730
690
730
570
600
mA
IDD3P
650
690
650
690
530
570
mA
IDD3N
810
890
810
890
650
730
mA
IDD4R
1770
2000
1770
2000
1450
1650
mA
IDD4W
1890
2200
1890
2200
1530
1690
mA
IDD5
1890
2200
1890
2200
1530
1690
mA
IDD6
Normal
32
32
32
32
32
32
mA
Low power
16
16
16
16
16
16
mA
IDD7
3100
3500
3100
3500
2450
2850
mA
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