參數(shù)資料
型號: V62C3181024
廠商: Mosel Vitelic, Corp.
英文描述: 3 Volt 128K X 8 Static RAM(3V 128Kx8靜態(tài)RAM)
中文描述: 3伏128K的× 8靜態(tài)RAM(3V的128Kx8靜態(tài)內(nèi)存)
文件頁數(shù): 5/12頁
文件大?。?/td> 60K
代理商: V62C3181024
MOSEL V ITELIC
V62C3181024
5
V62C3181024 Rev. 1.8 February 1999
AC Electrical Characteristics
(over all temperature ranges, V
CC
= 3.0V – 3.6V)
Read Cycle
Write Cycle
Parameter
Name
Parameter
-45
-70
Unit
Min.
Max.
Min.
Max.
t
RC
Read Cycle Time
45
70
ns
t
AA
Address Access Time
45
70
ns
t
ACS1
Chip Enable Access Time
45
70
ns
t
ACS2
Chip Enable Access Time
45
70
ns
t
OE
Output Enable to Output Valid
15
35
ns
t
CLZ1
Chip Enable to Output in Low Z
5
10
ns
t
CLZ2
Chip Enable to Output in Low Z
5
10
ns
t
OLZ
Output Enable to Output in Low Z
5
5
ns
t
CHZ
Chip Disable to Output in High Z
0
15
0
25
ns
t
OHZ
Output Disable to Output in High Z
0
15
0
25
ns
t
OH
Output Hold from Address Change
3
3
ns
t
PU
Chip Enable to Power Up Time
0
0
ns
t
PD
Chip Enable to Power Down Time
45
70
ns
Parameter
Name
Parameter
-45
-70
Unit
Min.
Max.
Min.
Max.
t
WC
Write Cycle Time
45
70
ns
t
CW1
Chip Enable to End of Write
35
60
ns
t
CW2
Chip Enable to End of Write
35
60
ns
t
AS
Address Setup Time
0
0
ns
t
AW
Address Valid to End of Write
35
60
ns
t
WP
Write Pulse Width
35
50
ns
t
WR
Write Recovery Time
0
0
ns
t
WHZ
Write to Output High-Z
0
15
0
25
ns
t
WLZ
Write to Output Low Z
3
5
ns
t
DW
Data Setup to End of Write
20
30
ns
t
DH
Data Hold from End of Write
0
0
ns
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