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參數(shù)資料
| 型號： | V62C1884096LL-85BI |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 85 ns, PBGA36 |
| 封裝： | 8 X 10 MM, CSP, BGA-36 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 48K |
| 代理商： | V62C1884096LL-85BI |
MOSEL VITELIC
V62C1884096
5
V62C1884096 Rev. 1.2 June 2000
Data Retention Characteristics
NOTES:
1.
tRC = Read Cycle Time
2.
TA = +25°C.
Low VCC Data Retention Waveform (1) (CE1 Controlled)
Key to Switching Waveforms
Symbol
Parameter
Power
Min.
Typ.(2)
Max.
Units
VDR
VCC for Data Retention
CE1 ≥ VCC – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V
1.0
—
2.3
V
ICCDR
Data Retention Current
CE1 ≥ VDR – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V, VDR = 1.0V
Com’lL
—
13
A
LL
—
0.5
1.5
Ind.
L
——
5
LL
——
2
tCDR
Chip Deselect to Data Retention Time
0
——
ns
tR
Operation Recovery Time (see Retention Waveform)
tRC
(1)
——
ns
VCC
Data Retention Mode
CE1 ≥ VCC – 0.2V
CE1
1.6V
1.8V
tCDR
tR
VDR ≥ 1V
1.8V
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE
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