參數(shù)資料
型號(hào)： V62/08627-01XE
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO8
封裝： GREEN, PLASTIC, MS-012AA, SOIC-8
文件頁(yè)數(shù)： 24/25頁(yè)
文件大小： 675K
代理商： V62/08627-01XE
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V OPERATION
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3 V OPERATION
SLLS882 – JUNE 2008....................................................................................................................................................................................................... www.ti.com
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Quiescent
0.3
0.5
ICC1
VCC1 supply current
VI = VCC or 0 V, No load
mA
25 Mbps
1
2
Quiescent
VI = VCC or 0 V, No load
4
6.5
ICC2
VCC2 supply current
mA
25 Mbps
VI = VCC or 0 V, No load
5
7.5
IOH = –4 mA, See Figure 1
VCC – 0.4
3
VOH
High-level output voltage
V
IOH = –20 A, See Figure 1
VCC – 0.1
3.3
IOL = 4 mA, See Figure 1
0.2
0.4
VOL
Low-level output voltage
V
IOL = 20 A, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
150
mV
IIH
High-level input current
IN at 2 V
10
A
IIL
Low-level input current
IN at 0.8 V
–10
High-impedance output
IOZ
ISO722, ISO722M
EN, IN at VCC
1
A
current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
25
40
kV/
s
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay, low-to-high-level output
20
tPHL
Propagation delay , high-to-low-level output
ISO72x
20
ns
tsk(p)
Pulse skew |tPHL – tPLH|
0.5
EN at 0 V,
tPLH
Propagation delay, low-to-high-level output
3
12
25
tPHL
Propagation delay, high-to-low-level output
ISO721M
3
12
25
tsk(p)
Pulse skew |tPHL – tPLH|
0.5
1
tsk(pp)
(1)
Part-to-part skew
5
ns
tr
Output signal rise time
2
EN at 0 V,
ns
tf
Output signal fall time
2
Sleep-mode propagation delay,
tpHZ
13
ns
high-level-to-high-mpedance output
Sleep-mode propagation delay,
tpZH
6
s
high-impedance-to-high-level output
ISO722
ISO722M
Sleep-mode propagation delay,
tpLZ
13
ns
low-level-to-high-impedance output
Sleep-mode propagation delay,
tpZL
6
s
high-impedance-to-low-level output
tfs
Failsafe output delay time from input power loss
3
s
100 Mbps NRZ data input, See Figure 6
2
ISO72x
100 Mbps unrestricted bit run length data
3
input, See Figure 6
tjit(PP)
Peak-to-peak eye-pattern jitter
ns
150 Mbps NRZ data input, See Figure 6
1
ISO72xM 150 Mbps unrestricted bit run length data
2
input, See Figure 6
(1)
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
8
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ISO721M-EP
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