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參數(shù)資料
| 型號(hào)： | UZZ9000 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Sensor Conditioning Electronic(傳感器調(diào)節(jié)芯片) |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 封裝： | SO-24 |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大?。?/td> | 69K |
| 代理商： | UZZ9000 |
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2000 May 19
8
Philips Semiconductors
Preliminary specification
Sensor Conditioning Electronic
UZZ9000
Trim interface
The serial interface used to switch the UZZ9000 into trim
mode consists of the two terminals SMODE (pin 10) and
DATA_CLK (pin 9). The structure of this protocol is shown
in Fig.4.
All signal levels at DATA_CLK and SMODE must be
selected according to the requirements listed in Table 3.
The following points must be taken into account with
regard to the asynchronous protocol.
The protocol starts with a falling edge at the SMODE,
whichmustoccuratahighDATA_CLKlevel.Thefollowing
five bits are used to code the message sent to the
UZZ9000. They are transferred via the SMODE and are
sampledwiththerisingedgeoftheDATA_CLK.Duringthe
fifthhighleveloutputofDATA_CLK(countedfromthestart
condition onwards), a rising edge must appear at the
SMODE and the DATA_CLK follows this with one more
change to low level in order to successfully complete the
protocol.
handbook, full pagewidth
MHB697
DATA_CLK
(input at pin 9)
SMODE
(input at pin 10)
TOUT
(output at pin 22)
1
2
3
4
5
stop
condition
status bit
start
condition
T1
T0
Fig.4 Protocol used to set UZZ9000 into trim mode.
Table 3
Definition of the trim interface signals
How to enter the trim mode
The status bits to be transmitted to the UZZ9000 are shown in Table 4. Note that a complete protocol has to be sent
before normal operation can be resumed. The trim mode can also be exited by resetting the device. After entering one
of the trim modes and provided there is a dynamic input signal, a square wave output is visible at the terminal T
OUT
(pin 22).
PARAMETER
MIN.
NOM.
MAX.
UNIT
UZZ9000 supply voltage
low level of DATA_CLK, SMODE
high level of DATA_CLK, SMODE
rise and fall time of DATA_CLK and SMODE signal
edges (10 to 90% V
DD
) and (90 to 10% V
DD
)
DATA_CLK frequency
4.5
0
95
8
5
5.5
5
100
V
%V
DD
%V
DD
ns
0.1
1
MHz
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