參數(shù)資料
型號(hào): USB2232-NU-03
廠商: SMSC Corporation
英文描述: 5th GENERATION HI-SPEED USB FLASH MEDIA AND CIR CONTROLLER WITH INTEGRATED CARD POWER FETs
中文描述: 第五代高速USB閃存介質(zhì)和CIR控制器,它集成卡功率場(chǎng)效應(yīng)管
文件頁數(shù): 16/26頁
文件大?。?/td> 937K
代理商: USB2232-NU-03
5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Revision 1.3 (07-12-05)
16
SMSC USB2231/USB2232
DATASHEET
MS
Card Insertion
MS_INS
IPU
This pin is the card detection signal from the MS device
to indicate, if the device is inserted.
This pin has an internally controlled weak pull-up
resistor.
MS
System CLK
MS_SCLK
O8
This pin is an output clock signal to the MS device.
The clock frequency is software configurable.
SD INTERFACE
SD
Data3-0
SD_DAT[3:0]
I/O8PU
These are bi-directional data signals.
These pins have internally controlled weak pull-up
resistors.
SD Clock
SD_CLK
O8
This is an output clock signal to SD/MMC device.
The clock frequency is software configurable.
SD Command
SD_CMD
I/O8PU
This is a bi-directional signal that connects to the CMD
signal of SD/MMC device.
This pin has an internally controlled weak pull-up
resistor.
SD
Write Protected
SD_nWP
IPD
This pin is an input signal with an internal weak pull-
down.
This pin has an internally controlled weak pull-down
resistor.
USB INTERFACE
USB Bus Data
USBDM
USBDP
IO-U
These pins connect to the USB bus data signals.
USB Transceiver
Bias
RBIAS
I
A 12.0k
,
±
1.0% resistor is attached from VSSA to this
pin, in order to set the transceiver’s internal bias
currents.
Analog Test
ATEST
AIO
This signal is used for testing the analog section of the
chip and should be connected to VDDA33 for normal
operation.
1.8v PLL Power
VDD18PLL
1.8v Power for the PLL
PLL Ground
Reference
VSSPLL
Ground Reference for 1.8v PLL power
3.3v Analog Power
VDDA33
3.3v Analog Power
Analog Ground
Reference
VSSA
Analog Ground Reference for 3.3v Analog Power.
Crystal
Input/External Clock
Input
XTAL1/
CLKIN
ICLKx
24Mhz Crystal or external 24/48 MHz clock input.
This pin can be connected to one terminal of the crystal
or can be connected to an external 24/48Mhz clock
when a crystal is not used.
Note:
The ‘MA[2:0] pins will be sampled while
nRESET is asserted, and the value will be
latched upon nRESET negation. This will
determine the clock source and value.
Table 6.1 USB2231/USB2232 Pin Descriptions
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
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