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參數(shù)資料
| 型號： | UPG154TB-E3 |
| 廠商： | NEC Corp. |
| 英文描述： | L-BAND SPDT SWITCH |
| 中文描述： | L波段單刀雙擲開關(guān) |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 94K |
| 代理商： | UPG154TB-E3 |
Data Sheet P13656EJ2V0DS00
3
μ
PG154TB
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, T
A
= +25
°
C, V
CONT1
= 3 V, V
CONT2
= 0 V or V
CONT1
= 0 V, V
CONT2
= 3 V, Z
O
= 50
,
V
DD
= 3.0 V, Off chip DC blocking capacitors value; 51 pF)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
f = 100 M to 1.0 GHz,
C
X
= 12.0 pF
0.30
0.65
Insertion Loss
L
INS
f = 2.0 GHz, C
X
= 2.0 pF
0.65
0.90
dB
f = 1.0 GHz, C
X
= 12.0 pF
20
24
f = 1.5 GHz, C
X
= 4.5 pF
22
Isolation
ISL
f = 2.0 GHz, C
X
= 2.0 pF
18
21
dB
Input Return Loss
RL
in
f = 100 M to 2.0 GHz,
C
X
= 2.0 pF
11
15
dB
Output Return Loss
RL
out
f = 100 M to 2.0 GHz,
C
X
= 2.0 pF
11
15
dB
Input Power at 0.1 dB
Compression Point
Note
P
in (0.1 dB)
f = 2.0 GHz, C
X
= 2.0 pF
26.5
dBm
Input Power at 1 dB
Compression Point
Note
P
in (1 dB)
f = 2.0 GHz, C
X
= 2.0 pF
27
30
dBm
Switching Speed
t
sw
30
ns
Control Current
I
CONT
V
CONT
= 3 V/0 V
2
10
μ
A
Note
P
in (1 dB)
and P
in (0.1 dB)
are measured the input power level when the insertion loss increase more 1 dB or 0.1
dB than that of linear range. All other characteristics are measured in linear range.
Cautions
1. The value of trap capacitor to improve the isolation performance should be chosen to
accommodate the operating frequency, band width, switching speed and the condition with
actual board of your system. The distance between IC’s No.2 pin and trap capacitor C
X
should be placed as shorter as possible to avoid parasitic parameters.
2. When the
μ
PG154TB is used, it is necessary to use DC blocking capacitors for No.1 (OUT1),
No.3 (OUT2) and No.5 (IN). The value of DC blocking capacitors should be chosen to
accommodate the operating frequency, band width, switching speed and the condition with
actual board of your system. The range of recommended DC blocking capacitor value is
less than 100 pF.
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