參數(shù)資料
型號(hào)： UPD98409
廠商： NEC Corp.
英文描述： ATM LIGHT SAR CONTROLLER
中文描述： 自動(dòng)柜員機(jī)燈特區(qū)控制器
文件頁(yè)數(shù)： 7/36頁(yè)
文件大?。?/td> 402K
代理商： UPD98409
7
μ
PD98409
(2/2)
Pin Name
Pin No.
I/O
I/O Level
Function
TENBL_B
136
O
TTL
Transmit Enable.
The TENBL_B signal indicates to a PHY device that data has been
output to Tx7 through Tx0 in the current clock cycle.
FULL_B/
TxCLAV
134
I
LV-TTL
PHY Buffer Full/Tx Cell Available.
This signal notifies the
μ
PD98409 that the input buffer of the PHY
device is full and that the device can receive no more data.
When the UTOPIA interface is in the octet-level handshake mode, the
PHY device inputs an inactive level to receive cell data. In the cell-
level handshake mode, the PHY device inputs a signal that indicates
that the PHY device can receive all the next one cell of data after the
current cell has been completely transferred.
TCLK
138
O
TTL
Transmit Clock.
This is a synchronization clock used to transfer cell data with the PHY
device at the transmission side. The system clock input to the
BUSCLK pin is output from this pin as is.
1.1.2 PHY device control interface
Pin Name
Pin No.
I/O
I/O Level
Function
PHRW_B
153
O
TTL
PHY Read/Write.
The
μ
PD98409 indicates the direction in which the PHY device is
controlled, by using PHRW_B.
1: Read
0: Write
PHOE_B
165
O
TTL
PHY Output Enable.
The
μ
PD98409 enables output from the PHY device by making
PHOE_B low
PHCE_B
166
O
TTL
PHY Chip Enable.
The
μ
PD98409 makes PHCE_B low to access a PHY device.
PHINT_B
152
I
LV-TTL
PHY Interrupt.
This is an interrupt input signal from a PHY device. The PHY device
indicates to the
μ
PD98409 that it has an interrupt source, by inputting
a low level to PHINT_B.
RSTOUT_B
232
O
TTL
Reset Output.
This is a signal to reset a PHY device. The
μ
PD98409 makes this pin
low for the duration of 11 to 22 clock cycles when a low level is input
to the RST_B pin or a software reset is executed.
CD7-CD0
154, 155,
157 - 159,
162 - 164
I/O
3-state
LV-TTL in
TTL out
PHY device data.
CD7 through CD0 constitute an 8-bit data bus. These pins are three-
state I/O pins. They are used to transfer data with a PHY device.
CA8-CA0
178 - 175,
173 - 170,
167
O
TTL
PHY device address.
CA8 through CA0 constitute a 9-bit address bus that outputs an
address to a PHY device during read/write operation.
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