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CHAPTER 1 GENERAL
30
User’s Manual U13952EJ3V1UD
1.6 Block Diagram
78K/0S
CPU core
ROM
(flash
memory)
RAM
VDD0
VDD1
VSS0
VSS1
IC
(VPP)
TI0/P24
8-bit timer
event/counter 00
P00 to P03
Port 0
P20 to P27
Port 2
P40 to P47
Port 4
P50 to P53
Port 5
P60 to P66
Port 6
P80 to P87
Port 8
P90 to P93
Port 9
System control
TI1/P25
8-bit timer
event/counter 01
TO2/P23
8-bit timer 02
TO5/P26
CPT5/P27
16-bit timer 50
Watch timer
Watchdog timer
Serial
interface
SCK/ASCK/P20
SI/RxD/P22
SO/TxD/P21
Comparator
CMPTOUT0/P23
CMPREF0/P61
CMPIN0/P60
A/D converter
ANI0/P60
ANI2/P62 to
ANI6/P66
ANI1/P61
AVDD
AVSS
AVREF
VLC0 to VLC2
BIAS
S0 to S15
S16/P93 to S19/P90
S20/P87 to S27/P80
COM0 to COM3
LCD
controller/driver
RESET
X1
X2
XT1
XT2
Interrupt
control
INTP0/P24
INTP1/P25
INTP2/P26
INTP3/P27
KR0/P40 to KR5/P45
Remarks 1. The internal ROM capacity varies depending on the product.
2. The parenthesized values apply to the
PD78F9418A.