
Preliminary User’s Manual U19291EJ1V0UD
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................... 61
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 67
3.1 Memory Space .............................................................................................................................. 67
3.1.1 Internal program memory space .......................................................................................................73
3.1.2 Mirror area ........................................................................................................................................75
3.1.3 Internal data memory space..............................................................................................................76
3.1.4 Special function register (SFR) area .................................................................................................77
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ........................77
3.1.6 Data memory addressing ..................................................................................................................78
3.2 Processor Registers .................................................................................................................... 82
3.2.1 Control registers................................................................................................................................82
3.2.2 General-purpose registers ................................................................................................................84
3.2.3 ES and CS registers .........................................................................................................................86
3.2.4 Special function registers (SFRs)......................................................................................................87
3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)............................92
3.3 Instruction Address Addressing ................................................................................................ 97
3.3.1 Relative addressing ..........................................................................................................................97
3.3.2 Immediate addressing.......................................................................................................................97
3.3.3 Table indirect addressing ..................................................................................................................98
3.3.4 Register direct addressing ................................................................................................................99
3.4 Addressing for Processing Data Addresses........................................................................... 100
3.4.1 Implied addressing ..........................................................................................................................100
3.4.2 Register addressing ........................................................................................................................100
3.4.3 Direct addressing ............................................................................................................................101
3.4.4 Short direct addressing ...................................................................................................................102
3.4.5 SFR addressing ..............................................................................................................................103
3.4.6 Register indirect addressing............................................................................................................104
3.4.7 Based addressing ...........................................................................................................................105
3.4.8 Based indexed addressing..............................................................................................................108
3.4.9 Stack addressing ............................................................................................................................109
CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 110
4.1 Port Functions ............................................................................................................................ 110
4.2 Port Configuration ..................................................................................................................... 113
4.2.1 Port 0 ..............................................................................................................................................114
4.2.2 Port 1 ..............................................................................................................................................116
4.2.3 Port 2 ..............................................................................................................................................119
4.2.4 Port 3 ..............................................................................................................................................121
4.2.5 Port 4 ..............................................................................................................................................125
4.2.6 Port 5 ..............................................................................................................................................128