參數(shù)資料
型號(hào)： UPD78F0361GK(S)-UET-A
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, LEAD FREE, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 25/32頁(yè)
文件大小： 3542K
代理商： UPD78F0361GK(S)-UET-A
CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual U17734EJ1V0UD
31
(b) TI51
This is an external count clock input pin to 8-bit timer/event counter 51.
(c) TO51
This is a timer output pin.
Caution
In the
μPD78F0363D be sure to pull the P31 pin down after reset to prevent malfunction.
Remark
P31 and P32 of the
μPD78F0363D can be used as on-chip debug mode setting pins (OCD1A,
OCD1B) when the on-chip debug function is used. For details, see CHAPTER 25
ON-CHIP
DEBUG FUNCTION (
μPD78F0363D ONLY).
2.2.5 P120 to P124 (port 12)
P120 to P124 function as a 5-bit I/O port. These pins also function as pins for external interrupt request input,
potential input for external low-voltage detection, resonator for main system clock connection, resonator for subsystem
clock connection, and external clock input. The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 to P124 function as a 5-bit I/O port. P120 to P124 can be set to input or output port using port mode
register 12 (PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option
register 12 (PU12).
(2) Control mode
P120 to P124 function as an external interrupt request input, potential input for external low-voltage detection,
resonator for main system clock connection, resonator for subsystem clock connection, and external clock input.
(a) INTP0
This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified.
(b) EXLVI
This is a potential input pin for external low-voltage detection.
(c) X1, X2
These are the pins for connecting a resonator for main system clock.
(d) EXCLK
This is an external clock input pin for main system clock.
(e) XT1, XT2
These are the pins for connecting a resonator for subsystem clock.
(f)
EXCLKS
This is an external clock input pin for subsystem clock.
Remark
X1 and X2 of the
μPD78F0363D can be used as on-chip debug mode setting pins (OCD0A,
OCD0B) when the on-chip debug function is used. For details, see CHAPTER 25
ON-CHIP
DEBUG FUNCTION (
μPD78F0363D ONLY).
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