參數(shù)資料
型號: UPD784021
廠商: NEC Corp.
英文描述: 16/8-BIT SINGLE-CHIP MICROCOMPUTER
中文描述: 16/8-BIT單片機(jī)
文件頁數(shù): 13/90頁
文件大?。?/td> 614K
代理商: UPD784021
13
m
PD784020, 784021
6.2 NON-PORT PINS (1/2)
Pin
I/O
Dual-function
Function
TO0-TO3
Output
P34-P37
Timer output
CI
Input
P23/INTP2
Input of a count clock for timer/counter 2
R
X
D
Input
P30/SI1
Serial data input (UART0)
R
X
D2
P13/SI2
Serial data input (UART2)
T
X
D
Output
P31/SO1
Serial data output (UART0)
T
X
D2
P14/SO2
Serial data output (UART2)
ASCK
Input
P25/INTP4/SCK1
Baud rate clock input (UART0)
ASCK2
P12/SCK2
Baud rate clock input (UART2)
SB0
I/O
P33/SO0
Serial data I/O (SBI)
SI0
Input
P27
Serial data input (3-wire serial I/O0)
SI1
P30/R
X
D
Serial data input (3-wire serial I/O1)
SI2
P13/R
X
D2
Serial data input (3-wire serial I/O2)
SO0
Output
P33/SB0
Serial data output (3-wire serial I/O0)
SO1
P31/T
X
D
Serial data output (3-wire serial I/O1)
SO2
P14/T
X
D2
Serial data output (3-wire serial I/O2)
SCK0
I/O
P32
Serial clock I/O (3-wire serial I/O0, SBI)
SCK1
P25/INTP4/ASCK
Serial clock I/O (3-wire serial I/O1)
SCK2
P12/ASCK2
Serial clock I/O (3-wire serial I/O2)
NMI
Input
P20
External interrupt request
INTP0
P21
Y
Input of a count clock for timer/counter 1
Y
Capture/trigger signal for CR11 or CR12
INTP1
P22
Y
Input of a count clock for timer/counter 2
Y
Capture/trigger signal for CR22
INTP2
P23/CI
Y
Input of a count clock for timer/counter 2
Y
Capture/trigger signal for CR21
INTP3
P24
Y
Input of a count clock for timer/counter 0
Y
Capture/trigger signal for CR02
INTP4
P25/ASCK/SCK1
INTP5
P26
Input of a conversion start trigger for A/D converter
AD0-AD7
I/O
Time multiplexing address/data bus (for connecting external memory)
A8-A15
Output
High-order address bus (for connecting external memory)
A16-A19
Output
P60-P63
High-order address bus during address expansion (for connecting external memory)
RD
Output
Strobe signal output for reading the contents of external memory
WR
Output
Strobe signal output for writing on external memory
WAIT
Input
P66/HLDRQ
Wait signal insertion
REFRQ
Output
P67/HLDAK
Refresh pulse output to external pseudo static memory
HLDRQ
Input
P66/WAIT
Input of bus hold request
HLDAK
Output
P67/REFRQ
Output of bus hold response
ASTB
Output
Latch timing output of time multiplexing address (A0-A7) (for
connecting external memory)
相關(guān)PDF資料
PDF描述
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