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| 型號： | UPD780146GC-XXX-8BT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 14 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 17/38頁 |
| 文件大小： | 4656K |
| 代理商： | UPD780146GC-XXX-8BT |
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P89LPC932A1_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 12 March 2007
48 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
10. Dynamic characteristics
Table 9.
Dynamic characteristics (12 MHz)
VDD = 2.4 V to 3.6 V unless otherwise specied.
Symbol
Parameter
Conditions
Variable clock
fosc =12MHz Unit
Min
Max
Min
Max
fOSC(RC)
internal RC oscillator frequency
7.189
7.557
7.189
7.557
MHz
fOSC(WD)
internal watchdog oscillator
frequency
280
480
280
480
kHz
fosc
oscillator frequency
0
12
-
MHz
Tcy(CLK)
clock cycle time
see Figure 23
83
-
ns
fCLKLP
low power select clock frequency
0
8
-
MHz
Glitch lter
tgr
glitch rejection
P1.5/RST pin
-
50
-
50
ns
any pin except
P1.5/RST
-
15
-
15
ns
tsa
signal acceptance
P1.5/RST pin
125
-
125
-
ns
any pin except
P1.5/RST
50
-
50
-
ns
External clock
tCHCX
clock HIGH time
see Figure 23
33
Tcy(CLK) tCLCX
33
-
ns
tCLCX
clock LOW time
see Figure 23
33
Tcy(CLK) tCHCX
33
-
ns
tCLCH
clock rise time
see Figure 23
-8
-
8
ns
tCHCL
clock fall time
see Figure 23
-8
-
8
ns
Shift register (UART mode 0)
tXLXL
serial port clock cycle time
see Figure 22
16Tcy(CLK)
-
1333
-
ns
tQVXH
output data set-up to clock rising
edge time
see Figure 22
13Tcy(CLK)
-
1083
-
ns
tXHQX
output data hold after clock rising
edge time
see Figure 22
-Tcy(CLK) + 20
-
103
ns
tXHDX
input data hold after clock rising
edge time
see Figure 22
-0
-
0
ns
tXHDV
input data valid to clock rising
edge time
see Figure 22
150
-
150
-
ns
SPI interface
fSPI
SPI operating frequency
slave
0
CCLK
6
0
2.0
MHz
master
-
CCLK
4
-
3.0
MHz
TSPICYC
SPI cycle time
slave
6
CCLK
-
500
-
ns
master
4
CCLK
-
333
-
ns
tSPILEAD
SPI enable lead time
2.0 MHz (slave)
250
-
250
-
ns
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