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參數(shù)資料
| 型號(hào)： | UPD780032AYGK |
| 廠商： | NEC Corp. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 12/70頁 |
| 文件大?。?/td> | 527K |
| 代理商： | UPD780032AYGK |
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12
μ
PD780031AY, 780032AY, 780033AY, 780034AY
Data Sheet U14045EJ1V0DS00
3.1 Port Pins (2/2)
Pin Name
I/O
Function
After
Reset
Alternate
Function
P70
I/O
Port 7
Input
TI00/TO0
P71
6-bit input/output port
TI01
P72
Input/output can be specified in 1-bit units.
TI50/TO50
P73
An on-chip pull-up resistor can be connected by means of software.
TI51/TO51
P74
PCL
P75
BUZ
3.2 Non-Port Pins (1/2)
Pin Name
I/O
Function
After
Reset
Alternate
Function
INTP0
Input
External interrupt request input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
Input
P00
INTP1
P01
INTP2
P02
INTP3
P03/ADTRG
SI30
Input
Serial interface serial data input
Input
P20
SO30
Output
Serial interface serial data output
Input
P21
SDA0
I/O
Serial interface serial data input/output
Input
P32
SCK30
I/O
Serial interface serial clock input/output
Input
P22
SCL0
P33
RxD0
Input
Serial data input for asynchronous serial interface
Input
P23
TxD0
Output
Serial data output for asynchronous serial interface
Input
P24
ASCK0
Input
Serial clock input for asynchronous serial interface
Input
P25
TI00
Input
External count clock input to 16-bit timer (TM0)
Capture trigger input to capture register (CR01) of 16-bit timer (TM0)
Input
P70/TO0
TI01
Capture trigger input to capture register (CR00) of 16-bit timer (TM0)
P71
TI50
External count clock input to 8-bit timer (TM50)
P72/TO50
TI51
External count clock input to 8-bit timer (TM51)
P73/TO51
TO0
Output
16-bit timer (TM0) output
Input
P70/TI00
TO50
8-bit timer (TM50) output (also used for 8-bit PWM output)
Input
P72/TI50
TO51
8-bit timer (TM51) output (also used for 8-bit PWM output)
P73/TI51
PCL
Output
Clock output (for trimming of main system clock and subsystem clock)
Input
P74
BUZ
Output
Buzzer output
Input
P75
AD0 to AD7
I/O
Lower address/data bus for expanding memory externally
Input
P40 to P47
A8 to A15
Output
Higher address bus for expanding memory externally
Input
P50 to P57
RD
Output
Strobe signal output for reading from external memory
Input
P64
WR
Strobe signal output for writing to external memory
P65
WAIT
Input
Wait insertion at external memory access
Input
P66
ASTB
Output
Strobe output that externally latches address information output to
ports 4 and 5 to access external memory
Input
P67
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