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參數(shù)資料
| 型號： | UPD77112 |
| 廠商： | NEC Corp. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 16位定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 23/80頁 |
| 文件大?。?/td> | 451K |
| 代理商： | UPD77112 |
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Data Sheet U12801EJ4V0DS00
23
μ
PD77110, 77111, 77112
2.4.4 Wait cycle register
The number of wait cycles to be inserted when the external data memory area is accessed can be specified in
advance by using a register (DWTR)
Note
. The number of wait cycles that can be set is 1, 3, or 7.
Note
This function is not available on the
μ
PD77111 because this DSP does not have an external data area.
3. CLOCK GENERATOR
The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and
supplies the generated clock to the internal units of the DSP.
For details of how to set the PLL multiple, refer to
4.2 Initializing PLL
,
8.1 Clock Control Options
, and
8.3.1
Settings related to clock control
.
Stop mode
PLL control circuit
Output divider
Halt divider
Halt mode
Internal
system clock
×
m
CLKOUT
CLKIN
÷
n
÷
l
4. RESET FUNCTION
When a low level of a specified width is input to the RESET pin, the device is initialized.
4.1 Hardware Reset
If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized.
If the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed
according to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the
instruction at address 0x200 of instruction memory (reset entry).
On power application, the RESET pin must be asserted active (low level) after 4 input clocks have been input with
the RESET pin in the inactive status (high level), after the supply voltage has reached the level of the operating
voltage. In other words, no power-ON reset function is available. On power application, the PLL must be initialized.
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