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參數(shù)資料
| 型號(hào)： | UPD77111F1 |
| 廠商： | NEC Corp. |
| 英文描述： | Multiconductor Cable; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| 中文描述： | 16位定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 16/80頁(yè) |
| 文件大?。?/td> | 451K |
| 代理商： | UPD77111F1 |
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Data Sheet U12801EJ4V0DS00
16
μ
PD77110, 77111, 77112
Host interface
Pin No.
Pin Name
100-pin
TQFP
80-pin
TQFP
80-pin
FBGA
I/O
Function
Shared by:
HA1
72
58
B9
Input
Specifies the register to be accessed by HD7
through HD0.
1: Accesses the host interface status
register (HST).
0: Accesses the host transmit data register
(HDT (out)) when read (HRD = 0), and
host receive data register (HDT (in))
when written (HWR = 0).
HA0
71
57
C8
Input
Specifies the register to be accessed by HD7
through HD0.
1: Accesses bits 15 through 8 of HST, HDT
(in), and HDT (out).
0: Accesses bits 7 through 0 of HST, HDT
(in), and HDT (out).
HCS
68
54
D7
Input
Chip select input
HRD
69
55
D8
Input
Host read input
HWR
70
56
C9
Input
Host write input
HRE
66
52
E6
Output
Host read enable output
HWE
67
53
D9
Output
Host write enable output
HD0 - HD7
63 - 56
49 - 42
E7, F7,
F9, F8,
G8, G9,
G7, H9
I/O
(3S)
8-bit host data bus
Remark
The pins marked “3S” under the heading “I/O” go into a high-impedance state when the host interface is
not being accessed.
I/O ports
Pin No.
Pin Name
100-pin
TQFP
80-pin
TQFP
80-pin
FBGA
I/O
Function
Shared by:
P0
55
39
J8
I/O
P1
54
38
H7
I/O
P2
53
37
F6
I/O
PLL0
Note
P3
52
36
J7
I/O
General-purpose I/O port
PLL1
Note
Note
Only the
μ
PD77110. The
μ
PD77111 and 77112 have no multiplexed pins.
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