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參數(shù)資料
| 型號(hào)： | UPD77110 |
| 廠商： | NEC Corp. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 16位定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 13/80頁(yè) |
| 文件大?。?/td> | 451K |
| 代理商： | UPD77110 |
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Data Sheet U12801EJ4V0DS00
13
μ
PD77110, 77111, 77112
1. PIN FUNCTION
Because the pin numbers differ depending on the package, refer to the diagram of the package to be used.
1.1 Pin Function Description
Power supply
Pin No.
Pin Name
100-pin
TQFP
80-pin
TQFP
80-pin
FBGA
I/O
Function
Shared by:
IV
DD
35, 77, 85
31, 63, 71
A5, A7, J5
Power to DSP core (+2.5 V)
EV
DD
25, 50,
64, 75,
100
10, 20,
40, 50,
60, 80
A1, A9,
E1, E9,
J1, J9
Power to I/O pins (+3 V)
GND
1, 26, 36,
51, 65,
76, 78, 86
1, 11, 21,
32, 41,
51, 61,
64, 72
A8, B2,
B5, B7,
E2, E8,
H5, H8,
J2
Ground
System control
Pin No.
Pin Name
100-pin
TQFP
80-pin
TQFP
80-pin
FBGA
I/O
Function
Shared by:
CLKIN
74
62
C7
Input
System clock input
CLKOUT
73
59
B8
Output
Internal system clock output
RESET
87
73
C4
Input
Internal system reset signal input
PLL0
53
Input
P2
PLL1
52
Input
P3
PLL2
49
Input
PLL multiple setting input (
μ
PD77110 only)
Determines the PLL multiple at reset as
followings:
PLL2: PLL1: PLL0:
000 : Selects PLL multiple of
×
1.
001 : Selects PLL multiple of
×
2.
010 : Selects PLL multiple of
×
3.
:
111 : Selects PLL multiple of
×
8.
These pins have no function on the
μ
PD77111 and 77112 .
WAKEUP
88
74
A4
Input
Stop mode release signal input.
When this pin is asserted active, the stop
mode is released. The function of this pin
can be activated or deactivated by a mask
option.
This pin is always valid on the
μ
PD77110 .
INT4
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