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參數(shù)資料
| 型號： | UPD75216 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 33/72頁 |
| 文件大?。?/td> | 530K |
| 代理商： | UPD75216 |
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33
μ
PD75216A
Table 8-1 Hardware Statuses after Reset
Counter (BT)
Mode register (BTM)
Counter (T0)
Modulo register (TMOD0)
Mode register (TM0)
Modulo register (MODH, MODL)
Mode register (TPGM)
Mode register (WM)
Shift register (SIO)
Mode register (SIOM)
Processor clock control register (PCC)
System clock control register (SCC)
Interrupt request flag (IRQ
×××
)
Interrupt enable flag (IE
×××
)
Priority select register (IPS)
INT0 and INT1 mode registers (IM0, IM1)
Output buffer
Output latch
Input/output mode register (PMGA, PMGB)
Output latch
Display mode register (DSPM)
Digit select register (DIGS)
Dimmer select register (DIMS)
Display data memory
Output buffer
Sets the low-order 6 bits of program
memory address 0000H to PC
13-8
and
the contents of address 0001H to PC
7-0
.
Hold
0
0
Sets bit 6 of program memory address
0000H to RBE and bit 7 to MBE.
Undefined
Hold
*1
Hold
0, 0
Undefined
0
0
FFH
0
Hold
0
0
Hold
Only bit 4 set to 1, other bits set to 0
0
0
Reset (0)
0
0
0, 0
Off
Clear (0)
0
Hold
0
1000B
0
Hold
Off
Hold
Program counter (PC)
Carry flag (CY)
Skip flag (SK0 to SK2)
Interrupt status flag (IST0, IST1)
Bank enable flags (MBE, RBE)
Stack pointer (SP)
Data memory (RAM)
General registers (X, A, H, L, D, E, B, C)
Bank select registers (MBS, RBS)
PSW
Basic interval
timer
Timer/event
counter
Timer/pulse
generator
Watch timer
Serial
interface
Clock
generator
Interrupt
Digital port
Port H
FIP controller/
driver
Power on flag (PONF)
Same as left
Undefined
0
0
Same as left
Undefined
Undefined
Undefined
0, 0
Undefined
0
0
FFH
0
Undefined
0
0
Undefined
Only bit 4 set to 1, other bits set to 0
0
0
Reset (0)
0
0
0, 0
Off
Clear (0)
0
Undefined
0
1000B
0
Undefined
Off
1 or undefined
*2
Hardware
RESET Input in Standby Mode
RESET Input upon
Power-on Reset or
in Operation
*
1.
Data of data memory addresses 0F8H to 0FDH becomes indeterminate by RESET input.
2.
1 upon power-on reset, indeterminate after RESET input in operation.
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