![](http://datasheet.mmic.net.cn/370000/UPD75008_datasheet_16740754/UPD75008_16.png)
μ
PD75004, 75006, 75008
16
4.
MEMORY CONFIGURATION
Program memory (ROM) ... 4096
×
8 bits (0000H-0FFFH) :
μ
PD75004
... 6016
×
8 bits (0000H-177FH) :
μ
PD75006
... 8064
×
8 bits (0000H-1F7FH) :
μ
PD75008
0000H-0001H: Vector table to which address from which program is started is written after reset
0002H-000BH: Vector table to which address from which program is started is written after interrupt
0020H-007FH: Table area referenced by GETI instruction
Data memory (RAM)
Data area .... 512
×
4 bits (000H–1FFH)
Peripheral hardware area .... 128
×
4 bits (F80H–FFFH)
7
6
5
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
Internal reset start address (upper 4 bits)
Internal reset start address (lower 8 bits)
INTBT/INT4 start address (upper 4 bits)
INTBT/INT4 start address (lower 8 bits)
INT0 start address (upper 4 bits)
INT0 start address (lower 8 bits)
INT1 start address (upper 4 bits)
INT1 start address (lower 8 bits)
INTCSI start address (upper 4 bits)
INTCSI start address (lower 8 bits)
INTT0 start address (upper 4 bits)
INTT0 start address (lower 8 bits)
000H
002H
004H
006H
008H
00AH
020H
07FH
080H
7FFH
800H
FFFH
GETI instruction reference table
0
CALLF
!faddr
instruction
entry
address
BRCD ! caddr
instruction
branch address
CALL ! addr
instruction
subroutine
entry address
BR $addr
instruction
relational
branch address
(–15 to –1,
+2 to +16)
Branch destination
address and
subroutine entry
address for
GETI instruction
Address
4
0
0
0
0
0
0
Fig. 4-1 Program Memory Map (
μ
PD75004)