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參數(shù)資料
| 型號： | UPD750004GBA-XXX-3BS-MTX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 8/86頁 |
| 文件大?。?/td> | 626K |
| 代理商： | UPD750004GBA-XXX-3BS-MTX |
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PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
14
Data Sheet U10738EJ3V2DS
4. Mk
Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION
4.1
DIFFERENCES BETWEEN Mk
Ι MODE AND Mk ΙΙ MODE
The CPU of the
PD750008 has two modes (Mk Ι mode and Mk ΙΙ mode) and which mode is used is selectable.
Bit 3 of the stack bank selection register (SBS) determines the mode.
Mk
Ι mode:
This mode has the upward compatibility with the
PD75008.
It can be used in the 75XL CPUs having a ROM of up to 16 KB.
Mk
ΙΙ mode: This mode is not compatible with the
PD75008.
It can be used in all 75XL CPUs, including those having a ROM of 16 KB or more.
Table 4-1 shows the differences between Mk
Ι mode and Mk ΙΙ mode.
Table 4-1
Differences between Mk
Ι Mode and Mk ΙΙ Mode
Caution Mk
ΙΙ mode can be used to support a program area larger than 16K bytes in the 75X series or 75XL
series. This mode enhances a software compatibility with products whose program area is larger
than 16K bytes. In Mk
ΙΙ mode, one more stack byte is required for execution of subroutine call
instructions per stack compared with Mk
Ι mode. When a CALL !addr or CALLF !faddr instruction
is executed, it takes one more machine cycle. Therefore, Mk
Ι mode should be used for applications
for which RAM efficiency or processing capabilities is more critical than a software compatibility.
Number of stack bytes in a
subroutine instruction
BRA !addr1 instruction
CALLA !addr1 instruction
CALL !addr instruction
CALLF !faddr instruction
2 bytes
None
3 machine cycles
2 machine cycles
3 bytes
Available
4 machine cycles
3 machine cycles
Mk
Ι mode
Mk
ΙΙ mode
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