參數(shù)資料
型號(hào): UPD70F3134AF1-EN4
廠商: NEC Corp.
英文描述: 32-Bit Single-Chip Microcontrollers
中文描述: 32位單芯片微控制器
文件頁(yè)數(shù): 50/99頁(yè)
文件大小: 528K
代理商: UPD70F3134AF1-EN4
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Application Note U17121EJ1V1AN
50
3.8.2 PCI bus interface timing
The PCI host bridge macro supports the following PCI bus interface timing.
(1) PCI bus master cycle timing
The timing of access from the CPU to the PCI device is shown below.
(a) Configuration read/write cycle, I/O read/write cycle, and memory read/write cycle
(i) Read cycle
Timing type: Configuration register read, internal I/O register read, memory read
Figure 3-11. Read Cycle
PCICLK
AD
H
DEVSEL#
TRDY#
FRAME#
STOP#
IRDY#
(ii) Write cycle
Timing type: Configuration register write, internal I/O register write, memory write
Figure 3-12. Write Cycle
AD
H
DEVSEL#
TRDY#
FRAME#
STOP#
IRDY#
PCICLK
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