
User’s Manual U12768EJ4V1UD
6
Major Revisions in This Edition (1/2)
Page
Description
Throughout
Addition of
PD703014B, 703014BY, 703015B, 703015BY, 70F3015B, and 70F3015BY
Deletion of
PD703014AGC, 703014AYGC, 703015AGC, and 703015AYGC
p. 27
Addition of Table 1-1 List of V850/SA1 Products
p. 28
Addition of description to minimum instruction execution time in 1.2 Features
p. 30
Deletion and addition of products in 1.4 Ordering Information
p. 31
Deletion and addition of products in 1.5 Pin Configuration
p. 35
Deletion of description in 1.6.2 (2) Bus control unit (BCU)
p. 38
Addition of Table 2-1 Pin I/O Buffer Power Supplies
p. 43
Modification of description in Table 2-2 Operating States of Pins in Each Operating Mode
p. 49
Modification of description in 2.3 (7) P60 to P65 (Port 6)
p. 53
Addition of 2.3 (13) CLKOUT (Clock out)
p. 55
Addition and modification of description in 2.4 Pin I/O Circuits and Recommended Connection of Unused
Pins
p. 58
Modification of 2.5 Pin I/O Circuits
p. 59
Addition of description to minimum instruction execution time in 3.1 Features
p. 63
Change of description in 3.2.2 (2) Program status word (PSW)
p. 80
Modification of Figure 3-16 Recommended Memory Map
p. 81
Addition of description in 3.4.8 Peripheral I/O registers
p. 86
Addition and modification of description in 3.4.9 Specific registers
p. 113
Addition of description in 5.2.4 Noise elimination of external interrupt request input pin
p. 114
Addition of description in 5.2.5 Edge detection function of external interrupt request input pin
p. 122
Addition to Cautions in 5.3.4 Interrupt control register (xxICn)
p. 125
Addition of Caution in 5.3.5 In-service priority register (ISPR)
p. 136
Addition of 5.8.1 Interrupt request valid timing after EI instruction
p. 137
Addition of 5.9 Bit Manipulation Instruction of Interrupt Control Register During DMA Transfer
p. 138
Modification of description in 6.1 (1) Main clock oscillator
p. 138
Modification of description in 6.1 (2) Subclock oscillator
p. 139
Modification of Figure 6-1 Clock Generator
p. 140
Addition to Notes in 6.3.1 (1) Processor clock control register (PCC)
p. 141
Modification of description in 6.3.1 (1) (b) Example of subclock operation
→ main clock operation setup
p. 142
Addition to Notes and Cautions in 6.3.1 (2) Power save control register (PSC)
p. 148
Modification of description in 6.4.4 (1) Settings and operating states
p. 151
Addition of 6.6 Notes on Power Save Function
p. 156
Modification of Caution in 7.1.3 (2) Capture/compare registers 00, 10 (CR00, CR10)
p. 157
Modification of Caution in 7.1.3 (3) Capture/compare registers 01, 11 (CR01, CR11)
p. 185
Change of Figure 7-27 Data Hold Timing of Capture Register
p. 185
Addition of 7.2.7 (6) (c) One-shot output function
p. 189
Addition of 7.3.1 Outline
The mark
shows major revised points.