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參數(shù)資料
| 型號： | UPD6345GS |
| 廠商： | NEC Corp. |
| 英文描述： | 8 BIT SERIAL IN/PARALLEL OUT DRIVER |
| 中文描述： | 8位串行/并行輸出驅(qū)動 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 79K |
| 代理商： | UPD6345GS |
μ
PD6345
2
PIN CONFIGURATION (Top View)
PIN IDENTIFICATION
Pin No.
Symbol
Pin name
Input/Output
Function
1
GND
Ground
—
Connection to Ground (GND) of system.
2
EN
Output Enable
Input
When this pin is low or open, all outputs are OFF, and data is output
during high.
3
LAT
Latch Enable
Input
When this pin is low or open, data is latched and data is through to
output during high.
4
SO
Serial data Output
Output
Serial data is output on positive-going transition of the clock.
In case of connection to cascade additional device (
μ
PD6345), this
pin will be connected to SIN terminal of additional device.
5 to 12
O
8
to O
1
Driver Output
Output
High Voltage and Current Driver Outputs.
13
SIN
Serial data Input
Input
Data is loaded to shift register on positive-going transition.
14
SCK
Clock
Input
Data of SIN is loaded to shift register on positive-going transition of
SCK. Also, serial data is output from SO on positive-going transition
of SCK.
15
RES
Reset
Input
When this pin is low or open, data of shift register is all cleared, and
this device operate normally during high.
16
V
DD
Power Supply
—
Normally supply 5 V.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
SS
EN
LAT
SO
O
8
O
7
O
6
O
5
V
DD
RES
SCK
SIN
O
1
O
2
O
3
O
4
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