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參數(shù)資料
| 型號： | UPD44324082F5-E37-EQ2 |
| 廠商： | NEC Corp. |
| 元件分類： | DRAM |
| 英文描述： | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 36M條位SRAM的2條DDRII字爆發(fā)運(yùn)作 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 361K |
| 代理商： | UPD44324082F5-E37-EQ2 |
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18
Data Sheet M16780EJ3V0DS
μ
PD44324082, 44324092, 44324182, 44324362
Read and Write Cycle
Parameter
Symbol
-E37
-E40
-E50
Unit
Note
(270 MHz)
(250 MHz)
(200 MHz)
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Clock
Average Clock cycle time (K, K#, C, C#)
Clock phase jitter (K, K#, C, C#)
Clock HIGH time (K, K#, C, C#)
Clock LOW time (K, K#, C, C#)
Clock (active high)
to Clock# (active low)
(K
→
K#, C
→
C#)
Clock# (active low)
to Clock (active high)
(K#
→
K, C#
→
C)
Clock to data clock
(K
→
C, K#
→
C#)
DLL lock time (K, C)
K static to DLL reset
TKHKH
TKC var
TKHKL
TKLKH
TKHK#H
TK#HKH
TKHCH
TKC lock
TKC reset
3.7
8.4
4.0
8.4
5.0
8.4
ns
1
–
0.2
–
0.2
–
0.2
ns
2
1.5
–
1.6
–
2.0
–
ns
1.5
–
1.6
–
2.0
–
ns
1.7
–
1.8
–
2.2
–
ns
1.7
–
1.8
–
2.2
–
ns
250 to 270 MHz
200 to 250 MHz
167 to 200 MHz
133 to 167 MHz
< 133 MHz
0
1.65
–
–
–
–
ns
0
1.8
0
1.8
–
–
0
2.3
0
2.3
0
2.3
0
2.8
0
2.8
0
2.8
0
3.55
0
3.55
0
3.55
1,024
–
1,024
–
1,024
–
Cycle
3
30
–
30
–
30
–
ns
Output Times
C, C# HIGH to output valid
C, C# HIGH to output hold
C, C# HIGH to echo clock valid
C, C# HIGH to echo clock hold
CQ, CQ# HIGH to output valid
CQ, CQ# HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
TCHQV
TCHQX
TCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
TCHQX1
–
0.45
–
0.45
–
0.45
ns
– 0.45
–
– 0.45
–
– 0.45
–
ns
–
0.45
–
0.45
–
0.45
ns
– 0.45
–
– 0.45
–
– 0.45
–
ns
–
0.3
–
0.3
–
0.35
ns
4
– 0.3
–
– 0.3
–
– 0.35
–
ns
4
–
0.45
–
0.45
–
0.45
ns
– 0.45
–
– 0.45
–
– 0.45
–
ns
Setup Times
Address valid to K rising edge
Synchronous load input (LD#),
read write input (R, W#) valid to
K rising edge
Data inputs and write data select
inputs (BWx#, NWx#) valid to
K, K# rising edge
TAVKH
TIVKH
TDVKH
0.5
–
0.5
–
0.6
–
ns
5
0.5
–
0.5
–
0.6
–
ns
5
0.35
–
0.35
–
0.4
–
ns
5
Hold Times
K rising edge to address hold
K rising edge to
synchronous load input (LD#),
read write input (R, W#) hold
K, K# rising edge to data inputs and
write data select inputs (BWx#, NWx#)
hold
TKHAX
TKHIX
TKHDX
0.5
–
0.5
–
0.6
–
ns
5
0.5
–
0.5
–
0.6
–
ns
5
0.35
–
0.35
–
0.4
–
ns
5
<R>
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| UPD44324082F5-E37-EQ2-A | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
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