參數(shù)資料
型號(hào)： UPD44324082F5-E37-EQ2-A
廠商： NEC Corp.
元件分類： DRAM
英文描述： 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
中文描述： 36M條位SRAM的2條DDRII字爆發(fā)運(yùn)作
文件頁(yè)數(shù)： 7/40頁(yè)
文件大?。?/td> 361K
代理商： UPD44324082F5-E37-EQ2-A
7
Data Sheet M16780EJ3V0DS
μ
PD44324082, 44324092, 44324182, 44324362
Pin Identification
(1/2)
Symbol
Description
A0
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the
rising edge of K. All transactions operate on a burst of two words (one clock period of bus activity). A0 is used
as the lowest order address bit permitting a random starting address within the burst operation on x18 and x36
devices. These inputs are ignored when device is deselected, i.e., NOP (LD# = H).
Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and K#. Output
data is synchronized to the respective C and C# data clocks or to K and K# if C and C# are tied to HIGH.
x8 device uses DQ0 to DQ7.
x9 device uses DQ0 to DQ8.
x18 device uses DQ0 to DQ17.
x36 device uses DQ0 to DQ35.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus
activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when R, W#
is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W# must meet the setup and hold times
around the rising edge of K.
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin Configurations
for signal to data relationships.
x8 device uses NW0#, NW1#.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx#, NWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data
on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of
C# is used as the output timing reference for first output data. The rising edge of C is used as the output
reference for second output data. Ideally, C# is 180 degrees out of phase with C. When use of K and K# as the
reference instead of C and C#, then fixed C and C# to High. Operation cannot be guaranteed unless C and C#
are fixed to High (i.e. toggle of C and C#)
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q
tristates.
If C and C# are stopped (if K and K# are stopped in the single clock mode), CQ and CQ# will also stop.
Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. DQ, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to
ground. The output impedance can be minimized by directly connect ZQ to V
DD
Q. This pin cannot be
connected directly to GND or left unconnected.
DLL Disable: When debugging the system or board, the operation can be performed at a clock frequency
slower than TKHKH (MAX.) without the DLL circuit being used, if DLL# = L. The AC/DC characteristics cannot
be guaranteed, however.
IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not
used in the circuit.
IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to V
SS
if the JTAG function is not used in the
circuit.
IEEE 1149.1 Test Output: 1.8V I/O level.
HSTL Input Reference Voltage: Nominally V
DD
Q/2. Provides a reference voltage for the input buffers.
Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics
and Operating Conditions for range.
DQ0 to DQxx
LD#
R, W#
BWx#
NWx#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
TMS
TDI
TCK
TDO
V
REF
VDD
VDDQ
相關(guān)PDF資料
PDF描述
UPD44324082F5-E40-EQ2-A 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44324082F5-E50-EQ2-A 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44324092F5-E37-EQ2 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44324092F5-E37-EQ2-A 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44324092F5-E40-EQ2-A 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD44324182BF5-E40-FQ1-A 制造商:Renesas Electronics Corporation 功能描述:RENUPD44324182BF5-E40-FQ1-A 36M-BIT(2M-W
UPD44324185BF5-E40-FQ1 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA
UPD44324362BF5-E40-FQ1 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA
UPD44324362BF5-E40-FQ1-A 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA
UPD44324365BF5-E40-FQ1 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA
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