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參數(shù)資料
| 型號： | UPD44165364F5-E50-EQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 18M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| 中文描述： | 1800萬位推出QDRII SRAM的4個字爆發(fā)運作 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 392K |
| 代理商： | UPD44165364F5-E50-EQ1 |
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8
Data Sheet M15825EJ7V
1
DS
μ
PD44165084, 44165184, 44165364
Truth Table
Operation
CLK
/R
/W
D or Q
WRITE cycle
L
→
H
H
L
Data in
Load address, input write data on two
Input data
D
A
(A+0)
D
A
(A+1)
D
A
(A+2)
D
A
(A+3)
consecutive K and /K rising edge
Input clock
K(t+1)
↑
/K(t+1)
↑
K(t+2)
↑
/K(t+2)
↑
READ cycle
L
→
H
L
X
Data out
Load address, read data on two
Output data
Q
A
(A+0)
Q
A
(A+1)
Q
A
(A+2)
Q
A
(A+3)
consecutive C and /C rising edge
Output clock
/C(t+1)
↑
C(t+2)
↑
/C(t+2)
↑
C(t+3)
↑
NOP (No operation)
L
→
H
H
H
D=X or Q=High-Z
STANDBY(Clock stopped)
Stopped
X
X
Previous state
Remarks 1.
H : High level, L : Low level,
×
: don’t care,
↑
: rising edge.
2.
Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges
except if C and /C are HIGH then data outputs are delivered at K and /K rising edges.
3.
/R and /W must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at
the rising edge of K.
4.
This device contains circuitry that will ensure the outputs will be in high impedance during power-up.
5.
Refer to state diagram and timing diagrams for clarification.
6.
It is recommended that K = /(/K) = C = /(/C) when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
7.
If /R was LOW to initiate the previous cycle, this signal becomes a don't care for this operation however it
is strongly recommended that this signal is brought HIGH as shown in the truth table.
8.
/W during write cycle and /R during read cycle were HIGH on previous K clock rising edge. Initiating
consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The
device will ignore the second request.
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