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參數(shù)資料
| 型號： | UPD3798CY |
| 廠商： | NEC Corp. |
| 英文描述： | 5348 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR |
| 中文描述： | 5348像素× 3彩色CCD線性圖像傳感器 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 107K |
| 代理商： | UPD3798CY |
μ
PD3798
5
DATA SHEET S14314EJ1V0DS00
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
V
OD
–0.3 to +15
V
Shift register clock voltage
V
φ
1
, V
φ
2
–0.3 to +8
V
Reset gate clock voltage
V
φ
RB
–0.3 to +8
V
Reset feed-through level clamp clock voltage
V
φ
CLB
–0.3 to +8
V
Transfer gate clock voltage
V
φ
TG1
to V
φ
TG3
–0.3 to +8
V
Operating ambient temperature
T
A
–25 to +60
°
C
Storage temperature
T
stg
–40 to +70
°
C
Caution
Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
°
C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Output drain voltage
V
OD
11.4
12.0
12.6
V
Shift register clock high level
V
φ
1H
, V
φ
2H
4.5
5.0
5.5
V
Shift register clock low level
V
φ
1L
, V
φ
2L
–0.3
0
+0.5
V
Reset gate clock high level
V
φ
RBH
4.5
5.0
5.5
V
Reset gate clock low level
V
φ
RBL
–0.3
0
+0.5
V
Reset feed-through level clamp clock high level
V
φ
CLBH
4.5
5.0
5.5
V
Reset feed-through level clamp clock low level
V
φ
CLBL
–0.3
0
+0.5
V
Transfer gate clock high level
V
φ
TG1H
to V
φ
TG3H
4.5
V
φ
1H
Note
V
φ
1H
Note
V
Transfer gate clock low level
V
φ
TG1L
to V
φ
TG3L
–0.3
0
+0.5
V
Data rate
f
φ
RB
–
1.0
5.0
MHz
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
),
Image lag can increase.
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| UPD3799CY | 制造商:NEC 制造商全稱:NEC 功能描述:5300 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR |
| UPD4011BC | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD4019BG | 制造商:Panasonic Industrial Company 功能描述:IC |
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