參數(shù)資料
型號(hào)： UPD3739D
廠商： NEC Corp.
英文描述： 5000 PIXELS CCD LINEAR IMAGE SENSOR
中文描述： 5000像素CCD線性圖像傳感器
文件頁(yè)數(shù)： 5/24頁(yè)
文件大?。?/td> 127K
代理商： UPD3739D
μ
PD3739
5
ABSOLUTE MAXIMUM RATINGS (T
A
= +25 C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
V
OD
–0.3 to +15
V
Shift register clock voltage
V
φ
1
, V
φ
2
–0.3 to +15
V
Reset gate clock voltage
V
φ
R1
, V
φ
R2
–0.3 to +15
V
Transfer gate clock voltage
V
φ
TG
–0.3 to +15
V
Operating ambient temperature
T
A
–25 to +55
C
Storage temperature
T
stg
–40 to +100
C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= –25 to +55 C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Output drain voltage
V
OD
11.4
12.0
12.6
V
Shift register clock high level
V
φ
1H
, V
φ
2H
4.5
5.0
5.5
V
Shift register clock low level
V
φ
1L
, V
φ
2L
–0.3
0
+0.5
V
Reset gate clock high level
V
φ
R1H
, V
φ
R2H
Note
4.5
5.0
5.5
V
Reset gate clock low level
V
φ
R1L
, V
φ
R2L
Note
–0.3
0
+0.5
V
Capacitance of reset gate clock pin external capacitor
C
EXT
φ
R
Non-polar type
800
1000
1200
pF
Transfer gate clock high level
V
φ
TGH
4.5
5.0
5.5
V
Transfer gate clock low level
V
φ
TGL
–0.3
0
+0.5
V
Data rate
2f
φ
R1
, 2f
φ
R2
0.5
2
40
MHz
Note
Input the reset gate clocks 1 and 2 (
φ
R1,
φ
R2) to pins 5 and 18, respectively, via an input resistor and a capacitor.
Use of a capacitor is indispensable. Refer to
APPLICATION CIRCUIT EXAMPLE
for the connection method.
The reset gate clock high level and low level at the IC pins (after passing through the external capacitor) varies
according to the IC, due to the on-chip automatic
φ
R level adjuster. The recommended operating conditions
of reset gate clocks 1, 2 (
φ
R1,
φ
R2) in the table above are for signals applied to the external capacitor.
Remark
φ
1 in the above tables represents
φ
11,
φ
12 and
φ
1L2.
φ
2 represents
φ
21,
φ
22 and
φ
2L1.
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