![](http://datasheet.mmic.net.cn/370000/UPD17134ACT-xxx_datasheet_16740627/UPD17134ACT-xxx_16.png)
- ix -
14-1
14-2
14-3
14-4
14-5
Interrupt Control Register ...................................................................................................................... 152
Interrupt Processing Procedure ............................................................................................................ 158
Return from Interrupt Processing .......................................................................................................... 159
Interrupt Accepting Timing (When INTE = 1, IP
×××
= 1) ..................................................................... 160
Example of Multi-interrupt ..................................................................................................................... 163
15-1
15-2
Block Diagram for the AC Zero Cross Detector ................................................................................... 167
Zero Cross Detection Signal ................................................................................................................. 168
16-1
16-2
Releasing HALT Mode ........................................................................................................................... 171
Releasing STOP Mode .......................................................................................................................... 175
17-1
17-2
17-3
17-4
17-5
Reset Block Configuration ..................................................................................................................... 181
Reset Operation ..................................................................................................................................... 181
Example of the Power-On Reset Operation ......................................................................................... 184
Example of the Power-Down Reset Operation..................................................................................... 186
Example of Reset Operation during the Period from Power-Down Reset to Power Recovery ......... 187
18-1
18-2
Procedure of Program Memory Writing ................................................................................................ 191
Procedure of Program Memory Reading .............................................................................................. 192
D-1
D-2
External Circuit of System Clock Oscillation Circuit............................................................................. 267
Example of Incorrect Oscillation Circuits .............................................................................................. 268
LIST OF FIGURES (3/3)
Figure No.
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