– vii –
LIST OF FIGURES (1/2)
Figure No.
Title
Page
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
Program Counter ...................................................................................................................
Value of the Program Counter after an Instruction Is Executed ............................................
Value in the Program Counter after Reset.............................................................................
Value in the Program Counter during Execution of a Direct Branch Instruction ....................
Value in the Program Counter during Execution of an Indirect Branch Instruction................
Value in the Program Counter during Execution of a Direct Subroutine Call .........................
Value in the Program Counter during Execution of an Indirect Subroutine Call.....................
Value in the Program Counter during Execution of a Return Instruction ...............................
19
20
20
20
21
21
21
22
4-1
4-2
4-3
Program Memory Map for the
μ
PD17120 Subseries ............................................................
Direct Subroutine Call (CALL addr) ........................................................................................
Table Reference (MOVT DBF, @AR) .....................................................................................
23
26
27
5-1
5-2
5-3
5-4
5-5
Configuration of Data Memory ..............................................................................................
System Register Configuration..............................................................................................
Data Buffer Configuration ......................................................................................................
General Register (GR) Configuration .....................................................................................
Port Register Configuration ...................................................................................................
31
32
32
33
33
6-1
Stack Configuration................................................................................................................
35
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
Allocation of System Register in Data Memory.....................................................................
System Register Configuration..............................................................................................
Address Register Configuration.............................................................................................
Address Register Used as a Peripheral Register ...................................................................
Window Register Configuration.............................................................................................
Bank Register Configuration ..................................................................................................
Index Register and Memory Pointer Configuration ...............................................................
Data Memory Address Modification by Index Register and Memory Pointer .......................
Example of Operation When MPE=0 and IXE=0...................................................................
Example of Operation When MPE=1 and IXE=0...................................................................
Example of Operation When MPE=0 and IXE=1...................................................................
Example of Operation When MPE=0 and IXE=1...................................................................
Example of Operation When MPE=0 and IXE=1 (Array Processing).....................................
General Register Pointer Configuration .................................................................................
General Register Configuration..............................................................................................
Program Status Word Configuration......................................................................................
Outline of Functions of the Program Status Word ................................................................
41
42
43
44
45
46
48
48
51
53
55
57
58
59
60
61
62
8-1
General Register Configuration..............................................................................................
70
9-1
9-2
Register File Configuration ....................................................................................................
Relationship Between the Register File and Data Memory...................................................
Accessing the Register File Using the PEEK and POKE Instructions ....................................
71
72
74
10-1
10-2
10-3
Allocation of the Data Buffer .................................................................................................
Data Buffer Configuration ......................................................................................................
Relationship Between the Data Buffer and Peripheral Hardware..........................................
79
80
80
11-1
Configuration of the ALU .......................................................................................................
86
12-1
12-2
12-3
Changes in port register due to execution of the CLR1 P0E1 instruction .............................
Input/Output Switching by Group I/O ....................................................................................
Bit I/O Port Control Register ..................................................................................................
112
113
114