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參數(shù)資料
| 型號： | UPD16682 |
| 廠商： | NEC Corp. |
| 英文描述： | CONN CABLE CLAMP METAL #18 IP68 |
| 中文描述： | 1 / 65稅LCD控制器/驅(qū)動器，片內(nèi)RAM |
| 文件頁數(shù)： | 18/56頁 |
| 文件大小： | 435K |
| 代理商： | UPD16682 |
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Data Sheet S13368EJ3V0DS00
18
μ
PD16682
6.5 Display Data Latch Circuit
The display data latch circuit is used for temporary storage of display data that has been output to the LCD driver
circuit from the display data RAM.
The commands that are used to set normal/inverted display modes, display ON/OFF status, and display all ON/OFF
status are commands that control data in this latch so that there is no modification of the data in the display data
RAM.
7. OSCILLATION CIRCUIT
This is a CR-type oscillation circuit that generates the display clock. The oscillation circuit is valid only when CLS =
H. When CLS = L, oscillation is stopped and the display clock is input via the CL pin.
8. DISPLAY TIMING GENERATOR
The display timing generator generates timing signals from the display clock to the line address circuit and the
display data latch circuit. Display data is latched into the display data latch circuit in synch with the display clock and
is output via segment driver output pins. Reading of the display data is completely independent of the MPU’s
accessing of the display data RAM. Consequently, there are no adverse effects (such as flicker) on the LCD panel
even when the display data RAM is accessed asynchronously in relation to the LCD contents.
The internal common timing and LCD’s AC conversion signal (FR) are both generated from the display clock. As is
shown in Figure 8
1, a drive waveform based on the two-frame AC drive method is generated for the LCD driver
circuit.
If a multiple set of
μ
PD16682 chips is used, the display timing signals (FR, CL, and /DOF) for the slave side must
be supplied from the master side.
Operation Mode
FR
CL
/DOF
Master (M,/S = H)
On-chip oscillation circuit is valid (CLS = H)
Output
Output
Output
On-chip oscillation circuit is invalid (CLS = L)
Output
Input
Output
Slave (M,/S = L)
On-chip oscillation circuit is invalid (CLS = H)
Input
Input
Input
On-chip oscillation circuit is invalid (CLS = L)
Input
Input
Input
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD16682N | 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| UPD16682P | 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| UPD16682W | 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| UPD16700 | 256-OUTPUT TFT-LCD GATE DRIVER |
| UPD16700N | DUSTCAP, METAL SZ22; Material:Zinc Alloy; Colour:Nickel Plated; Connector shell size:22; Voltage rating, AC:750V; Series:TRIM TRIO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD16682A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UPD16682A Data Sheet | Data Sheet[02/2001] |
| UPD16682AP | 制造商:NEC 制造商全稱:NEC 功能描述:1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| UPD16682AW | 制造商:NEC 制造商全稱:NEC 功能描述:1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| UPD16682N | 制造商:NEC 制造商全稱:NEC 功能描述:1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| UPD16682P | 制造商:NEC 制造商全稱:NEC 功能描述:1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
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