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參數(shù)資料
| 型號： | UPD16655N |
| 廠商： | NEC Corp. |
| 英文描述： | 240-OUTPUT TFT-LCD GATE DRIVER |
| 中文描述： | 240輸出的TFT - LCD柵極驅(qū)動器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 71K |
| 代理商： | UPD16655N |
Data Sheet S11950EJ2V0DS00
8
μ
PD16655
SWICHING CHARACTERISTICS (T
A
= –30 to +85 °C, V
DD1
= V
DD2
= 22 V, V
EE1
= V
EE2
= –9 V, V
SS
= 0 V,
V
CC
= 2.7 V to 5.5 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
t
PHL1
600
ns
Cascade Output Delay Time
t
PLH1
C
L
= 20 pF
600
ns
t
PHL2
700
ns
t
PLH2
C
L
= 220 pF
CLK
→
X
on
700
ns
t
d1
700
ns
Driver Output Delay Time
t
d2
C
L
= 220 pF, OE: L
→
H
C
L
= 220 pF, OE: H
→
L
700
ns
Output Rise Time
t
TLH
C
L
= 220 pF
300
ns
t
THL1
C
L
= 220 pF
300
ns
Output Fall Time
t
THL2
C
L
= 220 pF, V
EE2
= V
DD
– 15 V
400
ns
Input Capacitance
C
I
T
A
= 25°C
15
pF
Clock Frequency
f
CLK
In cascade connection
100
kHz
TIMING REQUIREMENTS (T
A
= –30 to 85 °C, V
DD1
= V
DD2
= 22 V, V
EE1
= V
EE2
= –9 V, V
SS
= 0 V,
V
CC
= 2.7 V to 5.5 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Clock Pulse Width
PW
CLK
1000
ns
Data Setup Time
t
setup
STVR(STVL)
↑
→
CLK
↑
100
ns
Data Hold Time
t
hold
CLK
↑
→
STVR(STVL)
↓
100
ns
Caution
Keep the time and fall time of the logic input to t
r
= t
f
= 20 ns (10 to 90 % of the rated values).
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