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參數(shù)資料
| 型號(hào)： | UPD16655N-XXX |
| 廠商： | NEC Corp. |
| 英文描述： | LCD Display Driver |
| 中文描述： | 液晶顯示驅(qū)動(dòng)程序 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 71K |
| 代理商： | UPD16655N-XXX |
Data Sheet S11950EJ2V0DS00
4
μ
PD16655
3. PIN FUNCTIONS
SYMBOL
PIN NAME
I/O
DESCRIPTION
O
1
to O
240
Driver Output
These pins output scan signals that drive the vertical
direction (gate lines) of a TFT-LCD. The output signals
change in synchronization with the rising edge of shift
clock CLK. The driver output amplitude is V
DD2
- V
EE2
.
V
SS
/V
CC
or
V
DD1
/V
EE1
(input)
This is the input of the internal shift register. The input
date is read at the rising edge of shift clock CLK, and
scan signals are output from the O
1
through O
120
pins.
The input level is a V
CC
/V
SS
or V
DD1
- V
EE1
level.
STVR
STVL
Start Pulse Input/Output
V
DD1
/V
EE1
(output)
This pin outputs a start pulse to the
μ
PD16655 at the
next stage when two or more
μ
PD16655s are connected
in cascade.
The pulse is output at the falling edge of the 240th clock
of shift clock CLK, and is cleared at the falling edge of the
241st clock.
R,/L
Shift Direction Select Input
V
SS
/V
CC
or
V
DD1
/V
EE1
R,/L = “H” (right shift): STVR
→
O
1
→
O
240
→
STVL
R,/L = “L” (left shift): STVL
→
O
240
→
O
1
→
STVR
CLK
Shift Clock Input
V
SS
/V
CC
This pin inputs a shift clock to the internal shift register.
The shift operation is performed in synchronization with
the rising edge of this input.
OE
Output Enable Input
V
SS
/V
CC
When this pin goes “H”, the driver output is fixed to “L”.
The shift register is not cleared, however. The internal
logic operates even when OE = “H”. OE is in
asynchronization with the clock.
V
DD1
Logic Positive Power Supply
10 V to 25 V
V
DD2
Driver Positive Power Supply
10 V to 25 V
V
CC
Reference Positive Power
Supply
3.0 to 5.5 V Reference voltage to level shifter LS.
V
SS
Reference Negative Power
Supply
Connect this pin to the ground of the system.
V
EE1
Logic Negative Power Supply
–21 V to –3 V
V
EE2
Driver Negative Power Supply
–21 V to V
DD2
– 15 V
Cautions 1. To prevent latch up, turn on power to V
CC
, V
EE1
-V
EE2
, V
DD1
-V
DD2
, and logic input in this order. Turn
off power in the reverse order. These power up/down sequence must be observed also during
transition period.
2. Insert a capacitor of about 0.1
μ
F between each power line, as shown below, to secure
noise margin such as V
IH
and V
IL
, because the internal logic operates on a high voltage
level. (V
DD
= V
DD1
= V
DD2
)
V
DD
V
CC
0.1
F
V
SS
V
EE
0.1
F
0.1
F
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