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參數(shù)資料
| 型號： | UPD16654 |
| 廠商： | NEC Corp. |
| 英文描述： | 150/154 OUTPUT TFT-LCD GATE DRIVE |
| 中文描述： | 一百五十四分之一百五十零輸出TFT - LCD柵驅(qū)動 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 72K |
| 代理商： | UPD16654 |
4
μ
PD16654
3. PIN FUNCTIONS
Pin Symbol
Pin Name
Description
O
1
to O
154
Driver output pins
Scan signal output pins that drive the gate electrode of a TFT-LCD.
The status of each output pin changes in synchronization with the rising edge
of shift clock CLK. The output voltage of the driver is V
DD2
to V
EE2
.
STVR
STVL
Start pulse input/output pin
Input/output pin of the internal shift register.
Start pulse signal is read at the rising edge of shift clock CLK and a scan
signal is output from the driver output pin. The interface of this terminal is
CMOS of 3.3 V.
When O
sel
signal is Low level, start pulse goes up to high level at the 154th
falling edge of shift clock CLK and goes down to low level at the 155th falling
edge.
And when O
sel
signal is High level, start pulse goes up to high level at the
150th falling edge of shift clock CLK and goes down to low level at the 151st
falling edge
.
The output level is V
CC
-V
SS
(logic level).
CLK
Shift clock input
Shift clock input for the internal shift register. The contents of internal shift
register is shifted at the rising edge of CLK.
R/L
Shift direction switching
input
Shift direction switching input pin of the internal shift register.
R/L = H (right shift) : STVR
→
O
1
→
O
2
··· O
153
→
O
154
→
STVL
R/L = L (left shift)
STVL
→
O
154
→
O
153
··· O
2
→
O
1
→
STVR
O
E1
O
E2
O
E3
Enable input
This pin fixes the driver output to the L level when it is high. However, the
shift register is not cleared. And, output enable actuation is asynchronous in
the clock. And, refer to “RELATIONS OF ENABLE INPUT AND OUTPUT
TERMINAL“.
O
sel
Number of output select
input
Selects the number of outputs.
O
sel
= L : 154 outputs (SVGA)
O
sel
= H: 150 outputs (VGA, XGA, SXGA)
When O
sel
= H (150 outputs), O
76
through O
79
outputs of the shift register are
fixed to the V
EE2
level. Fix this pin to V
CC
(V
DD2
) or V
SS
(V
EE1
) on TCP.
V
DD2
Positive power supply for
driver
Shared with internal logic and driver
V
CC
Reference power supply
3.3 V
±
0.3 V. Reference power supply for level shifter: LS
V
SS
Ground (GND)
Connect this pin to the system ground.
V
EE1
Negative power supply for
internal logic
Negative power supply for internal logic
V
EE2
Negative power supply for
driver
Negative power supply for driver
Caution
1. Power ON/OFF sequence
To prevent the
μ
PD16654 from damage due to latch up, turn on power in the order V
CC
V
EE2
and V
DD2
→
logic input. Turn off power in the reverse order. Observe these power
sequences even during transition period.
→
V
EE1
,
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD16654N | 150/154 OUTPUT TFT-LCD GATE DRIVE |
| UPD16676GF-3BA | 1/16, 1/32 DUTY LCD CONTROLLER/DRIVER |
| UPD16676 | 1/16, 1/32 DUTY LCD CONTROLLER/DRIVER |
| UPD16676P | 1/16, 1/32 DUTY LCD CONTROLLER/DRIVER |
| UPD16676W | 1/16, 1/32 DUTY LCD CONTROLLER/DRIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD16654N | 制造商:NEC 制造商全稱:NEC 功能描述:150/154 OUTPUT TFT-LCD GATE DRIVE |
| UPD16655 | 制造商:NEC 制造商全稱:NEC 功能描述:240-OUTPUT TFT-LCD GATE DRIVER |
| UPD16655N | 制造商:NEC 制造商全稱:NEC 功能描述:240-OUTPUT TFT-LCD GATE DRIVER |
| UPD16655N-XXX | 制造商:NEC 制造商全稱:NEC 功能描述:LCD Display Driver |
| UPD16661A | 制造商:NEC 制造商全稱:NEC 功能描述:160-OUTPUT LCD COLUMN SEGMENT DRIVER WITH RAM |
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