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參數(shù)資料
| 型號(hào)： | UPD16647N |
| 廠商： | NEC Corp. |
| 英文描述： | 402/384-OUTPUT TFT-LCD SOURCE DRIVER 64 GRAY SCALE |
| 中文描述： | 402/384-OUTPUT TFT - LCD的源驅(qū)動(dòng)64灰階 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | UPD16647N |
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Data Sheet S13607EJ2V0DS00
4
μ
PD16647
3. PIN DESCRIPTION
Pin Symbol
Pin Name
Description
S
1
to S
402/384
Driver output
Output 64 gray-scale analog voltages converted from digital signals.
Osel = H or open: 402 outputs (S
1
to S
402/384
)
Osel = L : 384 outputs (S
1
to S
192
, S
211/193
to S
402/384
)
S
193
to S
210
outputs are invalid in 384 outputs.
Inputs 18-bit-wide display gray scale data (6 bits) x 3 dots (RGB).
D
00
to D
05
Display data input
D
10
to D
15
D
X0
: LSB, D
X5
: MSB
D
20
to D
25
R,/L
Shift direction select input
This pin inputs/outputs start pulses in cascade mode.
Shift direction of shift register is as follows:
R,/L = H : STHR input, S
1
→
S
402
, STHL output
R,/L = L : STHL input, S
402
→
S
1
, STHR output
R,/L = H : Inputs start pulse
R,/L = L : Outputs start pulse
R/L = H : Outputs start pulse
R/L = L : Inputs start pulse
This pin can be used to finely control the bias current inside the output
amplifier. In cases when fine-control is necessary, connect this pin to V
DD2
using a resistor of 10 to 100k
(per IC). When this fine-control function is
not required, short-circuit this pin to V
DD2
. Refer to
7.
Bias Current Control
Function/Bcont
.
Inputs shift clock to shift register. Display data is loaded to data register at
rising edge of this pin. Start pulse output goes high at rising edge of 134th
clock after start pulse has been input, and serves as start pulse to driver in
next stage. 134th clock of driver in first stage serves as start pulse of driver
in next stage.
Contents of data register are latched at rising edge, transferred to D/A
converter, and output as analog voltage corresponding to display data.
Contents of internal shift register are cleared after STB has been input. One
pulse of this signal is input when
μ
PD16647 is started, and then device
operates normally.
For STB input timing, refer to
9. Switching Characteristics Waveform.
Selects number of outputs. This pin is internally pulled up to V
DD1
.
Osel = H or open : 402 outputs (S
1
to S
402/384
)
Osel = L : 384 outputs (S
1
to S
192
, S
211/193
to S
402/384
)
Inputs
γ
-corrected power from external source.
V
SS2
≤
V
9
≤
V
8
≤
V
7
≤
V
6
≤
V
5
≤
V
4
≤
V
3
≤
V
2
≤
V
1
≤
V
0
≤
V
DD2
or
V
SS2
≤
V
0
≤
V
1
≤
V
2
≤
V
3
≤
V
4
≤
V
5
≤
V
6
≤
V
7
≤
V
8
≤
V
9
≤
V
DD2
Maintain gray scale power supply during gray scale voltage output.
Input data can be inverted when display data is loaded.
INV = H : Inverts and loads input data.
INV = L : Does not invert input data.
3.3 V
±
0.3 V
STHR
Right shift start pulse I/O
STHL
Left shift start pulse I/O
Bcont
Bias control
CLK
Shift clock input
STB
Latch input
Osel
Selection of number of outputs
V
0
to V
9
γ
-corrected power supply
INV
Data inversion input
V
DD1
Logic circuit power supply
V
DD2
Driver circuit power supply
5.0 V
±
0.5 V
V
SS1
Logic ground
Ground
V
SS2
Driver ground
Ground
Caution
Be sure to turn on power in the order V
DD1
, logic input, V
DD2
, and gray scale power (V
0
to V
9
), and
turn off power in the reverse order, to prevent the
μ
PD16647 from being damaged by latchup. Be
sure to observe this power sequence even during a transition period.
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