參數(shù)資料
型號: UPD16634A
廠商: NEC Corp.
英文描述: 300-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64 GRAY SCALE
中文描述: 300輸出的TFT - LCD源驅(qū)動(dòng)程序完全兼容64灰階
文件頁數(shù): 5/20頁
文件大?。?/td> 115K
代理商: UPD16634A
Data Sheet S12595EJ2V0DS00
5
μ
PD16634A
4. PIN FUNCTIONS
Pin Symbol
Pin Name
Description
S
1
to S
300
D
00
to D
05
D
10
to D
15
D
20
to D
25
D
30
to D
35
D
40
to D
45
D
50
to D
55
R,/L
Driver output
Display data input
The D/A converted 64-gray-scale analog voltage is output
The display data is input with a width of 36 bits, viz., the gray scale data
(6 bits) by 6 dots (2 pixels).
D
X0
: LSB, D
X5
: MSB
Shift direction switching input
These refer to the start pulse input/output pins when cascades are
connected. The shift directions of the shift registers are as follows.
R,/L = H : STHR input, S
1
S
300
, STHL output
R,/L = L : STHL input, S
300
S
1
, STHR output
R,/L = H : Becomes the start pulse input pin.
R,/L = L : Becomes the start pulse output pin.
R,/L = H : Becomes the start pulse input pin.
R,/L = L : Becomes the start pulse output pin.
Refers to the shift register’s shift clock input. The display data is
incorporated into the data register at the rising edge. At the rising edge of
the 50th clock after the start pulse input, the start pulse output reaches the
high level, thus becoming the start pulse of the next-level driver. The initial-
level driver’s 50th clock becomes valid as the next-level driver’s start pulse
is input. If 52 clock pulses are input after input of the start pulse, input of
display data is halted automatically. The contents of the shift register are
cleared at the STB’s rising edge.
The contents of the data register are transferred to the latch at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the
driver. It is necessary to ensure input of one pulse per horizontal period.
POL = L ; The S
2n-1
output uses V
0
to V
4
as the reference supply; and the S
2n
output uses V
5
to V
9
as the reference supply.
POL = H ; The S
2n-1
output uses V
5
to V
9
as the reference supply; and the
S
2n
output uses V
0
to V
4
as the reference supply.
S
2n-1
indicates the odd output; and S
2n
indicates the even output. Input of
the POL signal is allowed the setup time (t
POL-STB
) with respect to STB’s
rising edge.
POL2 = H : Display data is inverted.
POL2 = L : Display data is not inverted.
Input the
γ
-corrected power supplies from outside by using operational
amplifier. Make sure to maintain the following relationships. During the gray
scale voltage output, be sure to keep the gray scale level power supply at a
constant level.
V
DD2
> V
0
> V
1
> V
2
> V
3
> V
4
> V
5
> V
6
> V
7
> V
8
> V
9
> V
SS2
Set it to open.
3.3 V
±
0.3 V
8.0 V
±
0.5 V
Grounding
Grounding
STHR
Right shift start pulse
input/output
Left shift start pulse input/output
STHL
CLK
Shift clock input
STB
Latch input
POL
Polarity input
POL2
Data inversion input
V
0
to V
9
γ
-corrected power supplies
TEST
V
DD1
V
DD2
V
SS1
V
SS2
Cautions 1. The power start sequence must be V
DD1
, logic input, and V
DD2
& V
0
to V
9
in that order. Reverse
this sequence to shut down.(Simultaneous power application to V
DD2
and V
0
to V
9
is possible.)
2. To stabilize the supply voltage, please be sure to insert 0.1
μ
F bypass capacitor between
V
DD1
-V
SS1
and V
DD2
-V
SS2
. Furthermore, for increase precision of the D/A converter, insertion of a
bypass capacitor of about 0.01
μ
F is also advised between the
γ
-corrected power supply
terminals(V
0
,V
1
,V
2
...,V
9
) and V
SS2
.
3. We recommend to use Operational Amplifier to lower input impedance of
γ
-corrected voltage.
Test pin
Logic circuit power supply
Driver circuit power supply
Logic ground
Driver ground
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD16634AN 制造商:NEC 制造商全稱:NEC 功能描述:300-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64 GRAY SCALE
UPD16634AN-XXX 制造商:NEC 制造商全稱:NEC 功能描述:LCD Display Driver
UPD16635 制造商:NEC 制造商全稱:NEC 功能描述:240-OUTPUT TFT-LCD SOURCE DRIVER
UPD16635N 制造商:NEC 制造商全稱:NEC 功能描述:240-OUTPUT TFT-LCD SOURCE DRIVER
UPD16635N-XXX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver