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參數(shù)資料
| 型號(hào)： | UPD16602N |
| 廠商： | NEC Corp. |
| 英文描述： | 312-OUTPUT TFT-LCD FULL COLOR DRIVER |
| 中文描述： | 312輸出的TFT - LCD全彩驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 134K |
| 代理商： | UPD16602N |
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5
μ
PD16602
3. PIN DESCRIPTION
Pin Symbol
S
1
to S
312
Pin Name
Description
Driver outputs
Output pins for sampled analog image signals. When driven with V
DD2
=
12.5 V, a
11.5 V
P-P
analog voltage whose input/output characteristic is gain 1 is output.
This pin reads the start pulse at the rising of CLK and starts sampling of analog
display signals in 12 channels simultaneously. The active edges of CLK are all
rising edges.
Analog image signal input pins. Please input analog display signals by inverting the
polarity for each display line.
CLK
Clock input
D
R0
to D
R3
D
G0
to D
G3
D
B0
to D
B3
Analog display
signal inputs
R/L
Shift direction
switching input
The shift direction of the shift register is as follows.
R/L = H (right shift) ; SPR input, S
1
→
S
312
, SPL output
R/L = L (left shift)
; SPL input, S
312
→
S
1
, SPR output
R/L = H (right shift) ; start pulse input pin
R/L = L (left shift)
; start pulse output pin
R/L = H (right shift) ; start pulse output pin
R/L = L (left shift)
; start pulse input pin
S/D = L; When PL/NL = H, Both odd number pin and even number pin samples
negative analog display signals and outputs positive analog signals from the
driver output.
When PL/NL = L, Both odd number pin and even number pin samples
positive analog display signals and outputs negative analog signals from the
driver output.
S/D = H; When PL/NL = H, Odd number pin samples negative analog display signals
and outputs positive analog signals from the driver output. Even number pin
samples positive analog display signals and outputs negative analog signals
from the driver output.
When PL/NL = L, Odd number pin samples positive analog display signals
and outputs negative analog signals from the driver output. Even number pin
samples negative analog display signals and outputs positive analog signals
from the driver output.
S/D = H; Complying with one side arrangement dot inverting.
S/D = L; Complying with both sides arrangement dot inverting.
This pin shuts off the output at the falling edge and then outputs analog display
signals at the rising. When HS = L, after the driver output pin goes to high impedance
this pin switches PL/NL and resets the internal hold capacity and output buffer to the
V
COM
level.
This pin shuts off the output buffer low current supply and increases the output
impedance. The LPC = “H” mode allows the static current consumption to be
reduced by approximately 20 %.
These pins control the current consumption of the output buffer by applying a
stabilized external power supply.
3.3 V
±
0.3 V
13.5 V
MAX.
13.5 V
MAX.
This pin applies the intermediate voltage of a stable LCD drive voltage from a voltage
follower, etc.
Logic ground
High voltage block (level shifter)
High voltage block (output buffer)
High voltage block (sample & hold)
“L” or left open
SPR
Start pulse input/
output
Start pulse input/
output
Polarity inversion
input
SPL
PL/NL
Note
S/D
Arrangement
switching input
Horizontal
synchronous input
HS
Note
LPC
Low power control
input
BIAS
1
BIAS
2
V
DD1
V
DD2(D)
V
DD2(A)
V
COM
Bias voltage inputs
Logic power supply
Driver power supply
Driver power supply
Common power
supply
Logic ground
Driver ground
Driver ground
Driver ground
Test pin
V
SS1
V
SS2(D)
V
SS2(A)
V
SS2(C)
TEST
Note
Sample & hold operation and reset operation of the output buffer capacitance and V
COM
level are performed
by the PL/NL and HS logic.
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