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Data Sheet S16472EJ1V0DS
7
μ
PD16347
3. PIN FUNCTIONS
Symbol
Pin Name
I/O
Description
/LBLK
Low blanking
Input
/LBLK
=
L: All output
=
L
/HBLK
High blanking
Input
/HBLK
=
L: All output
=
H
/LE
Latch enable
Input
Latch operation performed at the falling edge.
HZ
Output high impedance
Input
HZ = H: All output set to the high-impedance state
/CLR
Register clear
Input
/CLR = L: All shift register data cleared to the low level
A
1
to A
3 (6)
Data
Input
The A
1
to A
3 (6)
are Data input pins. The data shift direction is switched
inside the R,/L pin.
CLK
Clock
Input
SDS = H: Shift operation is executed at the rising and falling edges
SDS = L: Shift operation is executed at the rising edge
R,/L
Shift direction control
Input
The shift direction control pin of shift register. The shift directions of the
shift register are as follows.
R,/L = H (right shift):
SR
1
: A
1
→
S
1
...S
190
(SR
2
to SR
6
also shift in the same direction.)
R,/L = L (left shift):
SR
1
: A
1
→
S
190
...S
1
(SR
2
to SR
6
also shift in the same direction.)
Refer to
5. INTERNAL REGISTER.
IBS1,
IBS2
Input mode switch
Input
IBS1 = H, IBS2 = H: 6-bit (3-bit + 3-bit) input, Length of shift register: 32-bit
IBS1 = H, IBS2 = L: 6-bit input, Length of shift register: 32-bit
IBS1 = L, IBS2 = H: 3-bit input, Length of shift register: 64-bit
IBS1 = L, IBS2 = L: 4-bit input, Length of shift register: 48-bit
DET
Temperature detection
Output
The DET is N-ch open-drain output. Low level is output (N-ch transistor:
ON) via temperature detection.
SDS
Clock edge switch
Input
SDS = H: Shift operation is executed at the rising and falling edges of CLK
(double edge)
SDS = L: Shift operation is executed at the rising edge of CLK (single edge)
O
1
to O
192
High withstanding voltage
Output
70 V
V
DD1
Logic power supply
5 V
±
5%
V
DD2
Driver power supply
15 to 70 V
V
DD3
Temperature detection
power supply
5 V
±
10%
V
SS1
Logic ground
Connect to system ground
V
SS2
Driver ground
Connect to system ground
V
SS3
Temperature detection
ground
Connect to system ground
Caution In 3-bit and 4-bit input mode, unused input pins must be held at the low level or high level.